From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <abhinavk@codeaurora.org>
Cc: Jonathan Marek <jonathan@marek.ca>,
Stephen Boyd <sboyd@kernel.org>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org,
James Willcox <jwillcox@squareup.com>
Subject: [PATCH 6/7] drm/msm/mdp5: add perf blocks for holding fudge factors
Date: Tue, 25 May 2021 16:13:15 +0300 [thread overview]
Message-ID: <20210525131316.3117809-7-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20210525131316.3117809-1-dmitry.baryshkov@linaro.org>
From: James Willcox <jwillcox@squareup.com>
Prior downstream kernels had "fudge factors" in devicetree which would
be applied to things like interconnect bandwidth calculations. Bring
some of those values back here.
Signed-off-by: James Willcox <jwillcox@squareup.com>
[DB: changed _ff to _inefficiency, fixed patch description]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 35 ++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h | 7 +++++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
index 94ce62a26daf..9741544ffc35 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c
@@ -95,6 +95,11 @@ static const struct mdp5_cfg_hw msm8x74v1_config = {
[3] = INTF_HDMI,
},
},
+ .perf = {
+ .ab_inefficiency = 200,
+ .ib_inefficiency = 120,
+ .clk_inefficiency = 125
+ },
.max_clk = 200000000,
};
@@ -177,6 +182,11 @@ static const struct mdp5_cfg_hw msm8x74v2_config = {
[3] = INTF_HDMI,
},
},
+ .perf = {
+ .ab_inefficiency = 200,
+ .ib_inefficiency = 120,
+ .clk_inefficiency = 125
+ },
.max_clk = 320000000,
};
@@ -272,6 +282,11 @@ static const struct mdp5_cfg_hw apq8084_config = {
[3] = INTF_HDMI,
},
},
+ .perf = {
+ .ab_inefficiency = 200,
+ .ib_inefficiency = 120,
+ .clk_inefficiency = 105
+ },
.max_clk = 320000000,
};
@@ -339,6 +354,11 @@ static const struct mdp5_cfg_hw msm8x16_config = {
[1] = INTF_DSI,
},
},
+ .perf = {
+ .ab_inefficiency = 100,
+ .ib_inefficiency = 200,
+ .clk_inefficiency = 105
+ },
.max_clk = 320000000,
};
@@ -414,6 +434,11 @@ static const struct mdp5_cfg_hw msm8x36_config = {
[2] = INTF_DSI,
},
},
+ .perf = {
+ .ab_inefficiency = 100,
+ .ib_inefficiency = 200,
+ .clk_inefficiency = 105
+ },
.max_clk = 366670000,
};
@@ -509,6 +534,11 @@ static const struct mdp5_cfg_hw msm8x94_config = {
[3] = INTF_HDMI,
},
},
+ .perf = {
+ .ab_inefficiency = 100,
+ .ib_inefficiency = 100,
+ .clk_inefficiency = 105
+ },
.max_clk = 400000000,
};
@@ -617,6 +647,11 @@ static const struct mdp5_cfg_hw msm8x96_config = {
[3] = INTF_HDMI,
},
},
+ .perf = {
+ .ab_inefficiency = 100,
+ .ib_inefficiency = 200,
+ .clk_inefficiency = 105
+ },
.max_clk = 412500000,
};
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
index 1c50d01f15f5..6b03d7899309 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
@@ -76,6 +76,12 @@ struct mdp5_intf_block {
u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
};
+struct mdp5_perf_block {
+ u32 ab_inefficiency;
+ u32 ib_inefficiency;
+ u32 clk_inefficiency;
+};
+
struct mdp5_cfg_hw {
char *name;
@@ -93,6 +99,7 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block dsc;
struct mdp5_sub_block cdm;
struct mdp5_intf_block intf;
+ struct mdp5_perf_block perf;
uint32_t max_clk;
};
--
2.30.2
next prev parent reply other threads:[~2021-05-25 13:13 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-25 13:13 [PATCH 0/7] drm/msm/mdp5: add properties and bandwidth management Dmitry Baryshkov
2021-05-25 13:13 ` [PATCH 1/7] drm/msm/mdp5: use drm atomic helpers to handle base drm plane state Dmitry Baryshkov
2021-05-25 13:13 ` [PATCH 2/7] drm/msm/mdp5: use drm_plane_state for storing alpha value Dmitry Baryshkov
2021-05-25 13:13 ` [PATCH 3/7] drm/msm/mdp5: use drm_plane_state for pixel blend mode Dmitry Baryshkov
2021-05-25 13:13 ` [PATCH 4/7] drm/msm/mdp5: add support for alpha/blend_mode properties Dmitry Baryshkov
2021-05-25 13:13 ` [PATCH 5/7] drm/msm/mdp5: switch to standard zpos property Dmitry Baryshkov
2021-05-25 13:13 ` Dmitry Baryshkov [this message]
2021-05-25 13:13 ` [PATCH 7/7] drm/msm/mdp5: provide dynamic bandwidth management Dmitry Baryshkov
2021-05-25 17:15 ` kernel test robot
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