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[46.134.10.90]) by smtp.googlemail.com with ESMTPSA id v18sm20350733wro.18.2021.05.25.11.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 11:58:56 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id e44e7e8f; Tue, 25 May 2021 18:58:52 +0000 (UTC) Date: Tue, 25 May 2021 20:58:52 +0200 From: Bartosz Dudziak To: Stephan Gerhold Cc: Rob Herring , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , Daniel Lezcano , David Sterba , Jens Axboe , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH 2/2] cpuidle: qcom: Add SPM register data for APQ8026 and MSM8226 Message-ID: <20210525185852.GA2416@PackardBell> References: <20210513150150.51464-1-bartosz.dudziak@snejp.pl> <20210513150150.51464-2-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Thu, May 13, 2021 at 08:24:30PM +0200, Stephan Gerhold wrote: > Hi, > > On Thu, May 13, 2021 at 05:01:50PM +0200, Bartosz Dudziak wrote: > > Add APQ8026 and MSM8226 SoCs register data to SPM AVS Wrapper 2 (SAW2) > > power controller driver. > > > > Signed-off-by: Bartosz Dudziak > > --- > > drivers/cpuidle/cpuidle-qcom-spm.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c > > index adf91a6e4d..9711a98d68 100644 > > --- a/drivers/cpuidle/cpuidle-qcom-spm.c > > +++ b/drivers/cpuidle/cpuidle-qcom-spm.c > > @@ -87,6 +87,18 @@ static const struct spm_reg_data spm_reg_8974_8084_cpu = { > > .start_index[PM_SLEEP_MODE_SPC] = 3, > > }; > > > > +/* SPM register data for 8026, 8226 */ > > +static const struct spm_reg_data spm_reg_8x26_cpu = { > > + .reg_offset = spm_reg_offset_v2_1, > > + .spm_cfg = 0x0, > > + .spm_dly = 0x3C102800, > > + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, > > + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, > > + 0x80, 0x10, 0x26, 0x30, 0x0F }, > > + .start_index[PM_SLEEP_MODE_STBY] = 0, > > + .start_index[PM_SLEEP_MODE_SPC] = 5, > > +}; > > + > > static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { > > [SPM_REG_CFG] = 0x08, > > [SPM_REG_SPM_CTL] = 0x20, > > @@ -259,6 +271,10 @@ static struct spm_driver_data *spm_get_drv(struct platform_device *pdev, > > } > > > > static const struct of_device_id spm_match_table[] = { > > + { .compatible = "qcom,apq8026-saw2-v2.1-cpu", > > + .data = &spm_reg_8x26_cpu }, > > + { .compatible = "qcom,msm8226-saw2-v2.1-cpu", > > + .data = &spm_reg_8x26_cpu }, > > What is the reason for having a separate compatible for APQ8026? > > If the difference between MSM8226 and APQ8026 is similar to other qcom > SoCs (just lack of modem), both will end up using the same device tree > include anyway. Then it's easier to have both use qcom,msm8226-saw2-v2.1-cpu. > > Thanks, > Stephan You are right. There is no reason to have a seperate APQ8026 compatible because it will share the MSM8226 device tree. I will send later a v2 patch with only "qcom,msm8226-saw2-v2.1-cpu" option. Thanks, Bartosz