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* [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC
@ 2021-06-04 13:54 Roja Rani Yarubandi
  2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
                   ` (2 more replies)
  0 siblings, 3 replies; 17+ messages in thread
From: Roja Rani Yarubandi @ 2021-06-04 13:54 UTC (permalink / raw)
  To: agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
	saiprakash.ranjan, msavaliy, Roja Rani Yarubandi

Hi,

Broken the huge V2 patch into 3 smaller patches.

Roja Rani Yarubandi (3):
  arm64: dts: sc7280: Add QSPI node
  arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
  arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes

This patch depends on interconnect change [1]
[1] https://lore.kernel.org/patchwork/patch/1392104/

 arch/arm64/boot/dts/qcom/sc7280-idp.dts |  130 +-
 arch/arm64/boot/dts/qcom/sc7280.dtsi    | 2726 ++++++++++++++++++-----
 2 files changed, 2262 insertions(+), 594 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-04 13:54 [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC Roja Rani Yarubandi
@ 2021-06-04 13:54 ` Roja Rani Yarubandi
  2021-06-04 21:45   ` Stephen Boyd
  2021-06-06  3:55   ` Bjorn Andersson
  2021-06-04 13:54 ` [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Roja Rani Yarubandi
  2021-06-04 13:54 ` [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Roja Rani Yarubandi
  2 siblings, 2 replies; 17+ messages in thread
From: Roja Rani Yarubandi @ 2021-06-04 13:54 UTC (permalink / raw)
  To: agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
	saiprakash.ranjan, msavaliy, Roja Rani Yarubandi

Add QSPI DT node for SC7280 SoC.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
---
Changes in V3:
 - Broken the huge V2 patch into 3 smaller patches.
   1. QSPI DT nodes
   2. QUP wrapper_0 DT nodes
   3. QUP wrapper_1 DT nodes

Changes in V2:
 - As per Doug's comments removed pinmux/pinconf subnodes.
 - As per Doug's comments split of SPI, UART nodes has been done.
 - Moved QSPI node before aps_smmu as per the order.

 arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
 arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61 +++++++++++++++++++++++++
 2 files changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index 3900cfc09562..d0edffc15736 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -268,6 +268,22 @@ pmr735b_die_temp {
 		};
 };
 
+&qspi {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+
+		/* TODO: Increase frequency after testing */
+		spi-max-frequency = <25000000>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
+	};
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -278,6 +294,19 @@ &uart5 {
 
 /* PINCTRL - additions to nodes defined in sc7280.dtsi */
 
+&qspi_cs0 {
+	bias-disable;
+};
+
+&qspi_clk {
+	bias-disable;
+};
+
+&qspi_data01 {
+	/* High-Z when no transfers; nice to park the lines */
+	bias-pull-up;
+};
+
 &qup_uart5_default {
 	tx {
 		pins = "gpio46";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 6c9d5eb93f93..3047ab802cd2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
 			};
 		};
 
+		qspi_opp_table: qspi-opp-table {
+			compatible = "operating-points-v2";
+
+			opp-75000000 {
+				opp-hz = /bits/ 64 <75000000>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+			};
+
+			opp-150000000 {
+				opp-hz = /bits/ 64 <150000000>;
+				required-opps = <&rpmhpd_opp_svs>;
+			};
+
+			opp-300000000 {
+				opp-hz = /bits/ 64 <300000000>;
+				required-opps = <&rpmhpd_opp_nom>;
+			};
+		};
+
+		qspi: spi@88dc000 {
+			compatible = "qcom,qspi-v1";
+			reg = <0 0x088dc000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+				 <&gcc GCC_QSPI_CORE_CLK>;
+			clock-names = "iface", "core";
+			interconnects = <&gem_noc MASTER_APPSS_PROC 0
+					&cnoc2 SLAVE_QSPI_0 0>;
+			interconnect-names = "qspi-config";
+			power-domains = <&rpmhpd SC7280_CX>;
+			operating-points-v2 = <&qspi_opp_table>;
+			status = "disabled";
+		};
+
 		system-cache-controller@9200000 {
 			compatible = "qcom,sc7280-llcc";
 			reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
@@ -1186,6 +1222,31 @@ tlmm: pinctrl@f100000 {
 			gpio-ranges = <&tlmm 0 0 175>;
 			wakeup-parent = <&pdc>;
 
+			qspi_clk: qspi-clk {
+				pins = "gpio14";
+				function = "qspi_clk";
+			};
+
+			qspi_cs0: qspi-cs0 {
+				pins = "gpio15";
+				function = "qspi_cs";
+			};
+
+			qspi_cs1: qspi-cs1 {
+				pins = "gpio19";
+				function = "qspi_cs";
+			};
+
+			qspi_data01: qspi-data01 {
+				pins = "gpio12", "gpio13";
+				function = "qspi_data";
+			};
+
+			qspi_data12: qspi-data12 {
+				pins = "gpio16", "gpio17";
+				function = "qspi_data";
+			};
+
 			qup_uart5_default: qup-uart5-default {
 				pins = "gpio46", "gpio47";
 				function = "qup13";
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
  2021-06-04 13:54 [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC Roja Rani Yarubandi
  2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
@ 2021-06-04 13:54 ` Roja Rani Yarubandi
  2021-06-06  3:49   ` Bjorn Andersson
  2021-06-04 13:54 ` [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Roja Rani Yarubandi
  2 siblings, 1 reply; 17+ messages in thread
From: Roja Rani Yarubandi @ 2021-06-04 13:54 UTC (permalink / raw)
  To: agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
	saiprakash.ranjan, msavaliy, Roja Rani Yarubandi

Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
---
Changes in V3:
 - Broken the huge V2 patch into 3 smaller patches.
   1. QSPI DT nodes
   2. QUP wrapper_0 DT nodes
   3. QUP wrapper_1 DT nodes

Changes in V2:
 - As per Doug's comments removed pinmux/pinconf subnodes.
 - As per Doug's comments split of SPI, UART nodes has been done.
 - Moved QSPI node before aps_smmu as per the order.

 arch/arm64/boot/dts/qcom/sc7280-idp.dts |  97 ++-
 arch/arm64/boot/dts/qcom/sc7280.dtsi    | 750 +++++++++++++++++++++++-
 2 files changed, 835 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index d0edffc15736..f57458dbe763 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -292,6 +292,16 @@ &uart5 {
 	status = "okay";
 };
 
+&uart7 {
+	status = "okay";
+
+	/delete-property/interrupts;
+	interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+				<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+};
+
 /* PINCTRL - additions to nodes defined in sc7280.dtsi */
 
 &qspi_cs0 {
@@ -307,16 +317,87 @@ &qspi_data01 {
 	bias-pull-up;
 };
 
-&qup_uart5_default {
-	tx {
-		pins = "gpio46";
-		drive-strength = <2>;
-		bias-disable;
+&qup_uart5_tx {
+	drive-strength = <2>;
+	bias-disable;
+};
+
+&qup_uart5_rx {
+	drive-strength = <2>;
+	bias-pull-up;
+};
+
+&qup_uart7_cts {
+	/*
+	 * Configure a pull-down on CTS to match the pull of
+	 * the Bluetooth module.
+	 */
+	bias-pull-down;
+};
+
+&qup_uart7_rts {
+	/* We'll drive RTS, so no pull */
+	drive-strength = <2>;
+	bias-disable;
+};
+
+&qup_uart7_tx {
+	/* We'll drive TX, so no pull */
+	drive-strength = <2>;
+	bias-disable;
+};
+
+&qup_uart7_rx {
+	/*
+	 * Configure a pull-up on RX. This is needed to avoid
+	 * garbage data when the TX pin of the Bluetooth module is
+	 * in tri-state (module powered off or not driving the
+	 * signal yet).
+	 */
+	bias-pull-up;
+};
+
+&tlmm {
+	qup_uart7_sleep_cts: qup-uart7-sleep-cts {
+		pins = "gpio28";
+		function = "gpio";
+		/*
+		 * Configure a pull-down on CTS to match the pull of
+		 * the Bluetooth module.
+		 */
+		bias-pull-down;
+	};
+
+	qup_uart7_sleep_rts: qup-uart7-sleep-rts {
+		pins = "gpio29";
+		function = "gpio";
+		/*
+		 * Configure pull-down on RTS. As RTS is active low
+		 * signal, pull it low to indicate the BT SoC that it
+		 * can wakeup the system anytime from suspend state by
+		 * pulling RX low (by sending wakeup bytes).
+		 */
+		bias-pull-down;
+	};
+
+	qup_uart7_sleep_tx: qup-uart7-sleep-tx {
+		pins = "gpio30";
+		function = "gpio";
+		/*
+		 * Configure pull-up on TX when it isn't actively driven
+		 * to prevent BT SoC from receiving garbage during sleep.
+		 */
+		bias-pull-up;
 	};
 
-	rx {
-		pins = "gpio47";
-		drive-strength = <2>;
+	qup_uart7_sleep_rx: qup-uart7-sleep-rx {
+		pins = "gpio31";
+		function = "gpio";
+		/*
+		 * Configure a pull-up on RX. This is needed to avoid
+		 * garbage data when the TX pin of the Bluetooth module
+		 * is floating which may cause spurious wakeups.
+		 */
 		bias-pull-up;
 	};
 };
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3047ab802cd2..b783f5622a66 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -431,6 +431,25 @@ ipcc: mailbox@408000 {
 			#mbox-cells = <2>;
 		};
 
+		qup_opp_table: qup-opp-table {
+			compatible = "operating-points-v2";
+
+			opp-75000000 {
+				opp-hz = /bits/ 64 <75000000>;
+				required-opps = <&rpmhpd_opp_low_svs>;
+			};
+
+			opp-100000000 {
+				opp-hz = /bits/ 64 <100000000>;
+				required-opps = <&rpmhpd_opp_svs>;
+			};
+
+			opp-128000000 {
+				opp-hz = /bits/ 64 <128000000>;
+				required-opps = <&rpmhpd_opp_nom>;
+			};
+		};
+
 		qupv3_id_0: geniqup@9c0000 {
 			compatible = "qcom,geni-se-qup";
 			reg = <0 0x009c0000 0 0x2000>;
@@ -440,16 +459,424 @@ qupv3_id_0: geniqup@9c0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			ranges;
+			iommus = <&apps_smmu 0x123 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
+			interconnect-names = "qup-core";
 			status = "disabled";
 
+			i2c0: i2c@980000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00980000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c0_data_clk>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi0: spi@980000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00980000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart0: serial@980000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00980000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
+				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c1: i2c@984000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00984000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c1_data_clk>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi1: spi@984000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00984000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>, <&qup_spi1_cs_gpio>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart1: serial@984000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00984000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
+				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c2: i2c@988000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00988000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c2_data_clk>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi2: spi@988000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00988000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>, <&qup_spi2_cs_gpio>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart2: serial@988000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00988000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
+				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c3: i2c@98c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0098c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c3_data_clk>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi3: spi@98c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0098c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>, <&qup_spi3_cs_gpio>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart3: serial@98c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0098c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
+				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c4: i2c@990000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00990000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c4_data_clk>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi4: spi@990000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00990000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>, <&qup_spi4_cs_gpio>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart4: serial@990000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00990000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
+				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c5: i2c@994000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00994000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c5_data_clk>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi5: spi@994000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00994000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>, <&qup_spi5_cs_gpio>;
+				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
 			uart5: serial@994000 {
 				compatible = "qcom,geni-debug-uart";
 				reg = <0 0x00994000 0 0x4000>;
 				clock-names = "se";
 				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 				pinctrl-names = "default";
-				pinctrl-0 = <&qup_uart5_default>;
+				pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
 				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c6: i2c@998000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00998000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c6_data_clk>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi6: spi@998000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00998000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>, <&qup_spi6_cs_gpio>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart6: serial@998000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00998000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
+				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c7: i2c@99c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x0099c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c7_data_clk>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi7: spi@99c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x0099c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>, <&qup_spi7_cs_gpio>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart7: serial@99c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0099c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
+				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+				interconnect-names = "qup-core", "qup-config";
 				status = "disabled";
 			};
 		};
@@ -1247,9 +1674,324 @@ qspi_data12: qspi-data12 {
 				function = "qspi_data";
 			};
 
-			qup_uart5_default: qup-uart5-default {
-				pins = "gpio46", "gpio47";
-				function = "qup13";
+			qup_i2c0_data_clk:qup-i2c0-data-clk {
+				pins = "gpio0", "gpio1";
+				function = "qup00";
+			};
+
+			qup_i2c1_data_clk:qup-i2c1-data-clk {
+				pins = "gpio4", "gpio5";
+				function = "qup01";
+			};
+
+			qup_i2c2_data_clk:qup-i2c2-data-clk {
+				pins = "gpio8", "gpio9";
+				function = "qup02";
+			};
+
+			qup_i2c3_data_clk:qup-i2c3-data-clk {
+				pins = "gpio12", "gpio13";
+				function = "qup03";
+			};
+
+			qup_i2c4_data_clk:qup-i2c4-data-clk {
+				pins = "gpio16", "gpio17";
+				function = "qup04";
+			};
+
+			qup_i2c5_data_clk:qup-i2c5-data-clk {
+				pins = "gpio20", "gpio21";
+				function = "qup05";
+			};
+
+			qup_i2c6_data_clk:qup-i2c6-data-clk {
+				pins = "gpio24", "gpio25";
+				function = "qup06";
+			};
+
+			qup_i2c7_data_clk:qup-i2c7-data-clk {
+				pins = "gpio28", "gpio29";
+				function = "qup07";
+			};
+
+			qup_spi0_data_clk: qup-spi0-data-clk {
+				pins = "gpio0", "gpio1", "gpio2";
+				function = "qup00";
+			};
+
+			qup_spi0_cs: qup-spi0-cs {
+				pins = "gpio3";
+				function = "qup00";
+			};
+
+			qup_spi0_cs_gpio: qup-spi0-cs_gpio {
+				pins = "gpio3";
+				function = "gpio";
+			};
+
+			qup_spi1_data_clk: qup-spi1-data-clk {
+				pins = "gpio4", "gpio5", "gpio6";
+				function = "qup01";
+			};
+
+			qup_spi1_cs: qup-spi1-cs {
+				pins = "gpio7";
+				function = "qup01";
+			};
+
+			qup_spi1_cs_gpio: qup-spi1-cs_gpio {
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			qup_spi2_data_clk: qup-spi2-data-clk {
+				pins = "gpio8", "gpio9", "gpio10";
+				function = "qup02";
+			};
+
+			qup_spi2_cs: qup-spi2-cs {
+				pins = "gpio11";
+				function = "qup02";
+			};
+
+			qup_spi2_cs_gpio: qup-spi2-cs_gpio {
+				pins = "gpio11";
+				function = "gpio";
+			};
+
+			qup_spi3_data_clk: qup-spi3-data-clk {
+				pins = "gpio12", "gpio13", "gpio14";
+				function = "qup03";
+			};
+
+			qup_spi3_cs: qup-spi3-cs {
+				pins = "gpio15";
+				function = "qup03";
+			};
+
+			qup_spi3_cs_gpio: qup-spi3-cs_gpio {
+				pins = "gpio15";
+				function = "gpio";
+			};
+
+			qup_spi4_data_clk: qup-spi4-data-clk {
+				pins = "gpio16", "gpio17", "gpio18";
+				function = "qup04";
+			};
+
+			qup_spi4_cs: qup-spi4-cs {
+				pins = "gpio19";
+				function = "qup04";
+			};
+
+			qup_spi4_cs_gpio: qup-spi4-cs_gpio {
+				pins = "gpio19";
+				function = "gpio";
+			};
+
+			qup_spi5_data_clk: qup-spi5-data-clk {
+				pins = "gpio20", "gpio21", "gpio22";
+				function = "qup05";
+			};
+
+			qup_spi5_cs: qup-spi5-cs {
+				pins = "gpio23";
+				function = "qup05";
+			};
+
+			qup_spi5_cs_gpio: qup-spi5-cs_gpio {
+				pins = "gpio23";
+				function = "gpio";
+			};
+
+			qup_spi6_data_clk: qup-spi6-data-clk {
+				pins = "gpio24", "gpio25", "gpio26";
+				function = "qup06";
+			};
+
+			qup_spi6_cs: qup-spi6-cs {
+				pins = "gpio27";
+				function = "qup06";
+			};
+
+			qup_spi6_cs_gpio: qup-spi6-cs_gpio {
+				pins = "gpio27";
+				function = "gpio";
+			};
+
+			qup_spi7_data_clk: qup-spi7-data-clk {
+				pins = "gpio28", "gpio29", "gpio30";
+				function = "qup07";
+			};
+
+			qup_spi7_cs: qup-spi7-cs {
+				pins = "gpio31";
+				function = "qup07";
+			};
+
+			qup_spi7_cs_gpio: qup-spi7-cs_gpio {
+				pins = "gpio31";
+				function = "gpio";
+			};
+
+			qup_uart0_cts: qup-uart0-cts {
+				pins = "gpio0";
+				function = "qup00";
+			};
+
+			qup_uart0_rts: qup-uart0-rts {
+				pins = "gpio1";
+				function = "qup00";
+			};
+
+			qup_uart0_tx: qup-uart0-tx {
+				pins = "gpio2";
+				function = "qup00";
+			};
+
+			qup_uart0_rx: qup-uart0-rx {
+				pins = "gpio3";
+				function = "qup00";
+			};
+
+			qup_uart1_cts: qup-uart1-cts {
+				pins = "gpio4";
+				function = "qup01";
+			};
+
+			qup_uart1_rts: qup-uart1-rts {
+				pins = "gpio5";
+				function = "qup01";
+			};
+
+			qup_uart1_tx: qup-uart1-tx {
+				pins = "gpio6";
+				function = "qup01";
+			};
+
+			qup_uart1_rx: qup-uart1-rx {
+				pins = "gpio7";
+				function = "qup01";
+			};
+
+			qup_uart2_cts: qup-uart2-cts {
+				pins = "gpio8";
+				function = "qup02";
+			};
+
+			qup_uart2_rts: qup-uart2-rts {
+				pins = "gpio9";
+				function = "qup02";
+			};
+
+			qup_uart2_tx: qup-uart2-tx {
+				pins = "gpio10";
+				function = "qup02";
+			};
+
+			qup_uart2_rx: qup-uart2-rx {
+				pins = "gpio11";
+				function = "qup02";
+			};
+
+			qup_uart3_cts: qup-uart3-cts {
+				pins = "gpio12";
+				function = "qup03";
+			};
+
+			qup_uart3_rts: qup-uart3-rts {
+				pins = "gpio13";
+				function = "qup03";
+			};
+
+			qup_uart3_tx: qup-uart3-tx {
+				pins = "gpio14";
+				function = "qup03";
+			};
+
+			qup_uart3_rx: qup-uart3-rx {
+				pins = "gpio15";
+				function = "qup03";
+			};
+
+			qup_uart4_cts: qup-uart4-cts {
+				pins = "gpio16";
+				function = "qup04";
+			};
+
+			qup_uart4_rts: qup-uart4-rts {
+				pins = "gpio17";
+				function = "qup04";
+			};
+
+			qup_uart4_tx: qup-uart4-tx {
+				pins = "gpio18";
+				function = "qup04";
+			};
+
+			qup_uart4_rx: qup-uart4-rx {
+				pins = "gpio19";
+				function = "qup04";
+			};
+
+			qup_uart5_cts: qup-uart5-cts {
+				pins = "gpio20";
+				function = "qup05";
+			};
+
+			qup_uart5_rts: qup-uart5-rts {
+				pins = "gpio21";
+				function = "qup05";
+			};
+
+			qup_uart5_tx: qup-uart5-tx {
+				pins = "gpio22";
+				function = "qup05";
+			};
+
+			qup_uart5_rx: qup-uart5-rx {
+				pins = "gpio23";
+				function = "qup05";
+			};
+
+			qup_uart6_cts: qup-uart6-cts {
+				pins = "gpio24";
+				function = "qup06";
+			};
+
+			qup_uart6_rts: qup-uart6-rts {
+				pins = "gpio25";
+				function = "qup06";
+			};
+
+			qup_uart6_tx: qup-uart6-tx {
+				pins = "gpio26";
+				function = "qup06";
+			};
+
+			qup_uart6_rx: qup-uart6-rx {
+				pins = "gpio27";
+				function = "qup06";
+			};
+
+			qup_uart7_cts: qup-uart7-cts {
+				pins = "gpio28";
+				function = "qup07";
+			};
+
+			qup_uart7_rts: qup-uart7-rts {
+				pins = "gpio29";
+				function = "qup07";
+			};
+
+			qup_uart7_tx: qup-uart7-tx {
+				pins = "gpio30";
+				function = "qup07";
+			};
+
+			qup_uart7_rx: qup-uart7-rx {
+				pins = "gpio31";
+				function = "qup07";
 			};
 		};
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
  2021-06-04 13:54 [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC Roja Rani Yarubandi
  2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
  2021-06-04 13:54 ` [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Roja Rani Yarubandi
@ 2021-06-04 13:54 ` Roja Rani Yarubandi
  2021-06-06  3:53   ` Bjorn Andersson
  2 siblings, 1 reply; 17+ messages in thread
From: Roja Rani Yarubandi @ 2021-06-04 13:54 UTC (permalink / raw)
  To: agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
	saiprakash.ranjan, msavaliy, Roja Rani Yarubandi

Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
---
Changes in V3:
 - Broken the huge V2 patch into 3 smaller patches.
   1. QSPI DT nodes
   2. QUP wrapper_0 DT nodes
   3. QUP wrapper_1 DT nodes

Changes in V2:
 - As per Doug's comments removed pinmux/pinconf subnodes.
 - As per Doug's comments split of SPI, UART nodes has been done.
 - Moved QSPI node before aps_smmu as per the order.

 arch/arm64/boot/dts/qcom/sc7280-idp.dts |   4 +
 arch/arm64/boot/dts/qcom/sc7280.dtsi    | 751 ++++++++++++++++++++++++
 2 files changed, 755 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
index f57458dbe763..bdea9bf4eeca 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -288,6 +288,10 @@ &qupv3_id_0 {
 	status = "okay";
 };
 
+&qupv3_id_1 {
+	status = "okay";
+};
+
 &uart5 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b783f5622a66..348a34f3448e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -881,6 +881,437 @@ uart7: serial@99c000 {
 			};
 		};
 
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0 0x00ac0000 0 0x2000>;
+			clock-names = "m-ahb", "s-ahb";
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x43 0x0>;
+			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
+			interconnect-names = "qup-core";
+			status = "disabled";
+
+			i2c8: i2c@a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c8_data_clk>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi8: spi@a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>, <&qup_spi8_cs_gpio>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart8: serial@a80000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a80000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c9: i2c@a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c9_data_clk>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi9: spi@a84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>, <&qup_spi9_cs_gpio>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart9: serial@a84000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a84000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c10: i2c@a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c10_data_clk>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi10: spi@a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>, <&qup_spi10_cs_gpio>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart10: serial@a88000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a88000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c11: i2c@a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c11_data_clk>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi11: spi@a8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>, <&qup_spi11_cs_gpio>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart11: serial@a8c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a8c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c12: i2c@a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c12_data_clk>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi12: spi@a90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>, <&qup_spi12_cs_gpio>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart12: serial@a90000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a90000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c13: i2c@a94000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c13_data_clk>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi13: spi@a94000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>, <&qup_spi13_cs_gpio>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart13: serial@a94000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a94000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c14: i2c@a98000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c14_data_clk>;
+				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi14: spi@a98000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>, <&qup_spi14_cs_gpio>;
+				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart14: serial@a98000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a98000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
+				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			i2c15: i2c@a9c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_i2c15_data_clk>;
+				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+				interconnect-names = "qup-core", "qup-config",
+							"qup-memory";
+				status = "disabled";
+			};
+
+			spi15: spi@a9c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>, <&qup_spi15_cs_gpio>;
+				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+
+			uart15: serial@a9c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x00a9c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
+				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+				power-domains = <&rpmhpd SC7280_CX>;
+				operating-points-v2 = <&qup_opp_table>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+				interconnect-names = "qup-core", "qup-config";
+				status = "disabled";
+			};
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex", "syscon";
 			reg = <0 0x01f40000 0 0x40000>;
@@ -1714,6 +2145,46 @@ qup_i2c7_data_clk:qup-i2c7-data-clk {
 				function = "qup07";
 			};
 
+			qup_i2c8_data_clk:qup-i2c8-data-clk {
+				pins = "gpio32", "gpio33";
+				function = "qup08";
+			};
+
+			qup_i2c9_data_clk:qup-i2c9-data-clk {
+				pins = "gpio36", "gpio37";
+				function = "qup09";
+			};
+
+			qup_i2c10_data_clk:qup-i2c10-data-clk {
+				pins = "gpio40", "gpio41";
+				function = "qup10";
+			};
+
+			qup_i2c11_data_clk:qup-i2c11-data-clk {
+				pins = "gpio44", "gpio45";
+				function = "qup11";
+			};
+
+			qup_i2c12_data_clk:qup-i2c12-data-clk {
+				pins = "gpio48", "gpio49";
+				function = "qup12";
+			};
+
+			qup_i2c13_data_clk:qup-i2c13-data-clk {
+				pins = "gpio52", "gpio53";
+				function = "qup13";
+			};
+
+			qup_i2c14_data_clk:qup-i2c14-data-clk {
+				pins = "gpio56", "gpio57";
+				function = "qup14";
+			};
+
+			qup_i2c15_data_clk:qup-i2c15-data-clk {
+				pins = "gpio60", "gpio61";
+				function = "qup15";
+			};
+
 			qup_spi0_data_clk: qup-spi0-data-clk {
 				pins = "gpio0", "gpio1", "gpio2";
 				function = "qup00";
@@ -1834,6 +2305,126 @@ qup_spi7_cs_gpio: qup-spi7-cs_gpio {
 				function = "gpio";
 			};
 
+			qup_spi8_data_clk: qup-spi8-data-clk {
+				pins = "gpio32", "gpio33", "gpio34";
+				function = "qup08";
+			};
+
+			qup_spi8_cs: qup-spi8-cs {
+				pins = "gpio35";
+				function = "qup08";
+			};
+
+			qup_spi8_cs_gpio: qup-spi8-cs_gpio {
+				pins = "gpio35";
+				function = "gpio";
+			};
+
+			qup_spi9_data_clk: qup-spi9-data-clk {
+				pins = "gpio36", "gpio37", "gpio38";
+				function = "qup09";
+			};
+
+			qup_spi9_cs: qup-spi9-cs {
+				pins = "gpio39";
+				function = "qup09";
+			};
+
+			qup_spi9_cs_gpio: qup-spi9-cs_gpio {
+				pins = "gpio39";
+				function = "gpio";
+			};
+
+			qup_spi10_data_clk: qup-spi10-data-clk {
+				pins = "gpio40", "gpio41", "gpio42";
+				function = "qup10";
+			};
+
+			qup_spi10_cs: qup-spi10-cs {
+				pins = "gpio43";
+				function = "qup10";
+			};
+
+			qup_spi10_cs_gpio: qup-spi10-cs_gpio {
+				pins = "gpio43";
+				function = "gpio";
+			};
+
+			qup_spi11_data_clk: qup-spi11-data-clk {
+				pins = "gpio44", "gpio45", "gpio46";
+				function = "qup11";
+			};
+
+			qup_spi11_cs: qup-spi11-cs {
+				pins = "gpio47";
+				function = "qup11";
+			};
+
+			qup_spi11_cs_gpio: qup-spi11-cs_gpio {
+				pins = "gpio47";
+				function = "gpio";
+			};
+
+			qup_spi12_data_clk: qup-spi12-data-clk {
+				pins = "gpio48", "gpio49", "gpio50";
+				function = "qup12";
+			};
+
+			qup_spi12_cs: qup-spi12-cs {
+				pins = "gpio51";
+				function = "qup12";
+			};
+
+			qup_spi12_cs_gpio: qup-spi12-cs_gpio {
+				pins = "gpio51";
+				function = "gpio";
+			};
+
+			qup_spi13_data_clk: qup-spi13-data-clk {
+				pins = "gpio52", "gpio53", "gpio54";
+				function = "qup13";
+			};
+
+			qup_spi13_cs: qup-spi13-cs {
+				pins = "gpio55";
+				function = "qup13";
+			};
+
+			qup_spi13_cs_gpio: qup-spi13-cs_gpio {
+				pins = "gpio55";
+				function = "gpio";
+			};
+
+			qup_spi14_data_clk: qup-spi14-data-clk {
+				pins = "gpio56", "gpio57", "gpio58";
+				function = "qup14";
+			};
+
+			qup_spi14_cs: qup-spi14-cs {
+				pins = "gpio59";
+				function = "qup14";
+			};
+
+			qup_spi14_cs_gpio: qup-spi14-cs_gpio {
+				pins = "gpio59";
+				function = "gpio";
+			};
+
+			qup_spi15_data_clk: qup-spi15-data-clk {
+				pins = "gpio60", "gpio61", "gpio62";
+				function = "qup15";
+			};
+
+			qup_spi15_cs: qup-spi15-cs {
+				pins = "gpio63";
+				function = "qup15";
+			};
+
+			qup_spi15_cs_gpio: qup-spi15-cs_gpio {
+				pins = "gpio63";
+				function = "gpio";
+			};
+
 			qup_uart0_cts: qup-uart0-cts {
 				pins = "gpio0";
 				function = "qup00";
@@ -1993,6 +2584,166 @@ qup_uart7_rx: qup-uart7-rx {
 				pins = "gpio31";
 				function = "qup07";
 			};
+
+			qup_uart8_cts: qup-uart8-cts {
+				pins = "gpio32";
+				function = "qup08";
+			};
+
+			qup_uart8_rts: qup-uart8-rts {
+				pins = "gpio33";
+				function = "qup08";
+			};
+
+			qup_uart8_tx: qup-uart8-tx {
+				pins = "gpio34";
+				function = "qup08";
+			};
+
+			qup_uart8_rx: qup-uart8-rx {
+				pins = "gpio35";
+				function = "qup08";
+			};
+
+			qup_uart9_cts: qup-uart9-cts {
+				pins = "gpio36";
+				function = "qup09";
+			};
+
+			qup_uart9_rts: qup-uart9-rts {
+				pins = "gpio37";
+				function = "qup09";
+			};
+
+			qup_uart9_tx: qup-uart9-tx {
+				pins = "gpio38";
+				function = "qup09";
+			};
+
+			qup_uart9_rx: qup-uart9-rx {
+				pins = "gpio39";
+				function = "qup09";
+			};
+
+			qup_uart10_cts: qup-uart10-cts {
+				pins = "gpio40";
+				function = "qup10";
+			};
+
+			qup_uart10_rts: qup-uart10-rts {
+				pins = "gpio41";
+				function = "qup10";
+			};
+
+			qup_uart10_tx: qup-uart10-tx {
+				pins = "gpio42";
+				function = "qup10";
+			};
+
+			qup_uart10_rx: qup-uart10-rx {
+				pins = "gpio43";
+				function = "qup10";
+			};
+
+			qup_uart11_cts: qup-uart11-cts {
+				pins = "gpio44";
+				function = "qup11";
+			};
+
+			qup_uart11_rts: qup-uart11-rts {
+				pins = "gpio45";
+				function = "qup11";
+			};
+
+			qup_uart11_tx: qup-uart11-tx {
+				pins = "gpio46";
+				function = "qup11";
+			};
+
+			qup_uart11_rx: qup-uart11-rx {
+				pins = "gpio47";
+				function = "qup11";
+			};
+
+			qup_uart12_cts: qup-uart12-cts {
+				pins = "gpio48";
+				function = "qup12";
+			};
+
+			qup_uart12_rts: qup-uart12-rts {
+				pins = "gpio49";
+				function = "qup12";
+			};
+
+			qup_uart12_tx: qup-uart12-tx {
+				pins = "gpio50";
+				function = "qup12";
+			};
+
+			qup_uart12_rx: qup-uart12-rx {
+				pins = "gpio51";
+				function = "qup12";
+			};
+
+			qup_uart13_cts: qup-uart13-cts {
+				pins = "gpio52";
+				function = "qup13";
+			};
+
+			qup_uart13_rts: qup-uart13-rts {
+				pins = "gpio53";
+				function = "qup13";
+			};
+
+			qup_uart13_tx: qup-uart13-tx {
+				pins = "gpio54";
+				function = "qup13";
+			};
+
+			qup_uart13_rx: qup-uart13-rx {
+				pins = "gpio55";
+				function = "qup13";
+			};
+
+			qup_uart14_cts: qup-uart14-cts {
+				pins = "gpio56";
+				function = "qup14";
+			};
+
+			qup_uart14_rts: qup-uart14-rts {
+				pins = "gpio57";
+				function = "qup14";
+			};
+
+			qup_uart14_tx: qup-uart14-tx {
+				pins = "gpio58";
+				function = "qup14";
+			};
+
+			qup_uart14_rx: qup-uart14-rx {
+				pins = "gpio59";
+				function = "qup14";
+			};
+
+			qup_uart15_cts: qup-uart15-cts {
+				pins = "gpio60";
+				function = "qup15";
+			};
+
+			qup_uart15_rts: qup-uart15-rts {
+				pins = "gpio61";
+				function = "qup15";
+			};
+
+			qup_uart15_tx: qup-uart15-tx {
+				pins = "gpio62";
+				function = "qup15";
+			};
+
+			qup_uart15_rx: qup-uart15-rx {
+				pins = "gpio63";
+				function = "qup15";
+			};
 		};
 
 		apps_smmu: iommu@15000000 {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
@ 2021-06-04 21:45   ` Stephen Boyd
  2021-06-08  8:05     ` rojay
  2021-06-06  3:55   ` Bjorn Andersson
  1 sibling, 1 reply; 17+ messages in thread
From: Stephen Boyd @ 2021-06-04 21:45 UTC (permalink / raw)
  To: Roja Rani Yarubandi, agross, bjorn.andersson, robh+dt
  Cc: linux-arm-msm, devicetree, linux-kernel, Rajendra Nayak,
	saiprakash.ranjan, msavaliy, Roja Rani Yarubandi

Quoting Roja Rani Yarubandi (2021-06-04 06:54:37)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 3900cfc09562..d0edffc15736 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>                 };
>  };
>  
> +&qspi {
> +       status = "okay";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> +
> +       flash@0 {
> +               compatible = "jedec,spi-nor";
> +               reg = <0>;
> +
> +               /* TODO: Increase frequency after testing */

Is this going to change? Please set it to 37.5MHz if that's the max
supported.

> +               spi-max-frequency = <25000000>;
> +               spi-tx-bus-width = <2>;
> +               spi-rx-bus-width = <2>;
> +       };
> +};
> +
>  &qupv3_id_0 {
>         status = "okay";
>  };

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
  2021-06-04 13:54 ` [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Roja Rani Yarubandi
@ 2021-06-06  3:49   ` Bjorn Andersson
  2021-06-08  8:16     ` rojay
  0 siblings, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-06-06  3:49 UTC (permalink / raw)
  To: Roja Rani Yarubandi
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:

> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> ---
> Changes in V3:
>  - Broken the huge V2 patch into 3 smaller patches.
>    1. QSPI DT nodes
>    2. QUP wrapper_0 DT nodes
>    3. QUP wrapper_1 DT nodes
> 
> Changes in V2:
>  - As per Doug's comments removed pinmux/pinconf subnodes.
>  - As per Doug's comments split of SPI, UART nodes has been done.
>  - Moved QSPI node before aps_smmu as per the order.
> 
>  arch/arm64/boot/dts/qcom/sc7280-idp.dts |  97 ++-
>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 750 +++++++++++++++++++++++-
>  2 files changed, 835 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index d0edffc15736..f57458dbe763 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -292,6 +292,16 @@ &uart5 {
>  	status = "okay";
>  };
>  
> +&uart7 {
> +	status = "okay";
> +
> +	/delete-property/interrupts;
> +	interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
> +				<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
> +};
> +
>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>  
>  &qspi_cs0 {
> @@ -307,16 +317,87 @@ &qspi_data01 {
>  	bias-pull-up;
>  };
>  
> -&qup_uart5_default {
> -	tx {
> -		pins = "gpio46";

Commit message says "add stuff", but somehow uart5 is no longer
gpio46/47 and these gpios are no longer specified.

Can you roll this in a way where the giant patch actually _only_ adds
a whole bunch of stuff?

> -		drive-strength = <2>;
> -		bias-disable;
> +&qup_uart5_tx {
> +	drive-strength = <2>;
> +	bias-disable;
> +};
> +

Regards,
Bjorn

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
  2021-06-04 13:54 ` [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Roja Rani Yarubandi
@ 2021-06-06  3:53   ` Bjorn Andersson
  2021-06-08  8:10     ` rojay
  0 siblings, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-06-06  3:53 UTC (permalink / raw)
  To: Roja Rani Yarubandi
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:

> Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> ---
> Changes in V3:
>  - Broken the huge V2 patch into 3 smaller patches.
>    1. QSPI DT nodes
>    2. QUP wrapper_0 DT nodes
>    3. QUP wrapper_1 DT nodes
> 
> Changes in V2:
>  - As per Doug's comments removed pinmux/pinconf subnodes.
>  - As per Doug's comments split of SPI, UART nodes has been done.
>  - Moved QSPI node before aps_smmu as per the order.
> 
>  arch/arm64/boot/dts/qcom/sc7280-idp.dts |   4 +
>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 751 ++++++++++++++++++++++++
>  2 files changed, 755 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index f57458dbe763..bdea9bf4eeca 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -288,6 +288,10 @@ &qupv3_id_0 {
>  	status = "okay";
>  };
>  
> +&qupv3_id_1 {
> +	status = "okay";
> +};
> +
>  &uart5 {
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index b783f5622a66..348a34f3448e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -881,6 +881,437 @@ uart7: serial@99c000 {
>  			};
>  		};
>  
> +		qupv3_id_1: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0 0x00ac0000 0 0x2000>;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			iommus = <&apps_smmu 0x43 0x0>;
> +			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
> +			interconnect-names = "qup-core";

We used to have interconnect votes for the wrapper, but I recently
merged patches that dropped these for sc7180, so please conclude which
way this should be.

The rest looks good.

Regards,
Bjorn

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
  2021-06-04 21:45   ` Stephen Boyd
@ 2021-06-06  3:55   ` Bjorn Andersson
  2021-06-08  8:07     ` rojay
  1 sibling, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-06-06  3:55 UTC (permalink / raw)
  To: Roja Rani Yarubandi
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:

> Add QSPI DT node for SC7280 SoC.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> ---
> Changes in V3:
>  - Broken the huge V2 patch into 3 smaller patches.
>    1. QSPI DT nodes
>    2. QUP wrapper_0 DT nodes
>    3. QUP wrapper_1 DT nodes
> 
> Changes in V2:
>  - As per Doug's comments removed pinmux/pinconf subnodes.
>  - As per Doug's comments split of SPI, UART nodes has been done.
>  - Moved QSPI node before aps_smmu as per the order.
> 
>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61 +++++++++++++++++++++++++
>  2 files changed, 90 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> index 3900cfc09562..d0edffc15736 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>  		};
>  };
>  
> +&qspi {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> +
> +	flash@0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +
> +		/* TODO: Increase frequency after testing */
> +		spi-max-frequency = <25000000>;
> +		spi-tx-bus-width = <2>;
> +		spi-rx-bus-width = <2>;
> +	};
> +};
> +
>  &qupv3_id_0 {
>  	status = "okay";
>  };
> @@ -278,6 +294,19 @@ &uart5 {
>  
>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>  
> +&qspi_cs0 {
> +	bias-disable;
> +};
> +
> +&qspi_clk {
> +	bias-disable;
> +};
> +
> +&qspi_data01 {
> +	/* High-Z when no transfers; nice to park the lines */
> +	bias-pull-up;
> +};
> +
>  &qup_uart5_default {
>  	tx {
>  		pins = "gpio46";
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 6c9d5eb93f93..3047ab802cd2 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
>  			};
>  		};
>  
> +		qspi_opp_table: qspi-opp-table {

This node doesn't represents anything on the mmio bus, so it shouldn't
live in in /soc. Can't you move it into &qspi?

Regards,
Bjorn

> +			compatible = "operating-points-v2";
> +
> +			opp-75000000 {
> +				opp-hz = /bits/ 64 <75000000>;
> +				required-opps = <&rpmhpd_opp_low_svs>;
> +			};
> +
> +			opp-150000000 {
> +				opp-hz = /bits/ 64 <150000000>;
> +				required-opps = <&rpmhpd_opp_svs>;
> +			};
> +
> +			opp-300000000 {
> +				opp-hz = /bits/ 64 <300000000>;
> +				required-opps = <&rpmhpd_opp_nom>;
> +			};
> +		};
> +
> +		qspi: spi@88dc000 {
> +			compatible = "qcom,qspi-v1";
> +			reg = <0 0x088dc000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> +				 <&gcc GCC_QSPI_CORE_CLK>;
> +			clock-names = "iface", "core";
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 0
> +					&cnoc2 SLAVE_QSPI_0 0>;
> +			interconnect-names = "qspi-config";
> +			power-domains = <&rpmhpd SC7280_CX>;
> +			operating-points-v2 = <&qspi_opp_table>;
> +			status = "disabled";
> +		};

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-04 21:45   ` Stephen Boyd
@ 2021-06-08  8:05     ` rojay
  0 siblings, 0 replies; 17+ messages in thread
From: rojay @ 2021-06-08  8:05 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: agross, bjorn.andersson, robh+dt, linux-arm-msm, devicetree,
	linux-kernel, Rajendra Nayak, saiprakash.ranjan, msavaliy

On 2021-06-05 03:15, Stephen Boyd wrote:
> Quoting Roja Rani Yarubandi (2021-06-04 06:54:37)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index 3900cfc09562..d0edffc15736 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>>                 };
>>  };
>> 
>> +&qspi {
>> +       status = "okay";
>> +       pinctrl-names = "default";
>> +       pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>> +
>> +       flash@0 {
>> +               compatible = "jedec,spi-nor";
>> +               reg = <0>;
>> +
>> +               /* TODO: Increase frequency after testing */
> 
> Is this going to change? Please set it to 37.5MHz if that's the max
> supported.
> 

Okay, will set it to 37.5MHz.

Thanks,
Roja

>> +               spi-max-frequency = <25000000>;
>> +               spi-tx-bus-width = <2>;
>> +               spi-rx-bus-width = <2>;
>> +       };
>> +};
>> +
>>  &qupv3_id_0 {
>>         status = "okay";
>>  };

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-06  3:55   ` Bjorn Andersson
@ 2021-06-08  8:07     ` rojay
  2021-07-06  9:19       ` rojay
  0 siblings, 1 reply; 17+ messages in thread
From: rojay @ 2021-06-08  8:07 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On 2021-06-06 09:25, Bjorn Andersson wrote:
> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> 
>> Add QSPI DT node for SC7280 SoC.
>> 
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> ---
>> Changes in V3:
>>  - Broken the huge V2 patch into 3 smaller patches.
>>    1. QSPI DT nodes
>>    2. QUP wrapper_0 DT nodes
>>    3. QUP wrapper_1 DT nodes
>> 
>> Changes in V2:
>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>>  - As per Doug's comments split of SPI, UART nodes has been done.
>>  - Moved QSPI node before aps_smmu as per the order.
>> 
>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61 
>> +++++++++++++++++++++++++
>>  2 files changed, 90 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index 3900cfc09562..d0edffc15736 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>>  		};
>>  };
>> 
>> +&qspi {
>> +	status = "okay";
>> +	pinctrl-names = "default";
>> +	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>> +
>> +	flash@0 {
>> +		compatible = "jedec,spi-nor";
>> +		reg = <0>;
>> +
>> +		/* TODO: Increase frequency after testing */
>> +		spi-max-frequency = <25000000>;
>> +		spi-tx-bus-width = <2>;
>> +		spi-rx-bus-width = <2>;
>> +	};
>> +};
>> +
>>  &qupv3_id_0 {
>>  	status = "okay";
>>  };
>> @@ -278,6 +294,19 @@ &uart5 {
>> 
>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>> 
>> +&qspi_cs0 {
>> +	bias-disable;
>> +};
>> +
>> +&qspi_clk {
>> +	bias-disable;
>> +};
>> +
>> +&qspi_data01 {
>> +	/* High-Z when no transfers; nice to park the lines */
>> +	bias-pull-up;
>> +};
>> +
>>  &qup_uart5_default {
>>  	tx {
>>  		pins = "gpio46";
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 6c9d5eb93f93..3047ab802cd2 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
>>  			};
>>  		};
>> 
>> +		qspi_opp_table: qspi-opp-table {
> 
> This node doesn't represents anything on the mmio bus, so it shouldn't
> live in in /soc. Can't you move it into &qspi?
> 
> Regards,
> Bjorn
> 

Sure, will move it into qspi node.

Thanks,
Roja

>> +			compatible = "operating-points-v2";
>> +
>> +			opp-75000000 {
>> +				opp-hz = /bits/ 64 <75000000>;
>> +				required-opps = <&rpmhpd_opp_low_svs>;
>> +			};
>> +
>> +			opp-150000000 {
>> +				opp-hz = /bits/ 64 <150000000>;
>> +				required-opps = <&rpmhpd_opp_svs>;
>> +			};
>> +
>> +			opp-300000000 {
>> +				opp-hz = /bits/ 64 <300000000>;
>> +				required-opps = <&rpmhpd_opp_nom>;
>> +			};
>> +		};
>> +
>> +		qspi: spi@88dc000 {
>> +			compatible = "qcom,qspi-v1";
>> +			reg = <0 0x088dc000 0 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>> +				 <&gcc GCC_QSPI_CORE_CLK>;
>> +			clock-names = "iface", "core";
>> +			interconnects = <&gem_noc MASTER_APPSS_PROC 0
>> +					&cnoc2 SLAVE_QSPI_0 0>;
>> +			interconnect-names = "qspi-config";
>> +			power-domains = <&rpmhpd SC7280_CX>;
>> +			operating-points-v2 = <&qspi_opp_table>;
>> +			status = "disabled";
>> +		};

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
  2021-06-06  3:53   ` Bjorn Andersson
@ 2021-06-08  8:10     ` rojay
  0 siblings, 0 replies; 17+ messages in thread
From: rojay @ 2021-06-08  8:10 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On 2021-06-06 09:23, Bjorn Andersson wrote:
> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> 
>> Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
>> 
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> ---
>> Changes in V3:
>>  - Broken the huge V2 patch into 3 smaller patches.
>>    1. QSPI DT nodes
>>    2. QUP wrapper_0 DT nodes
>>    3. QUP wrapper_1 DT nodes
>> 
>> Changes in V2:
>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>>  - As per Doug's comments split of SPI, UART nodes has been done.
>>  - Moved QSPI node before aps_smmu as per the order.
>> 
>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts |   4 +
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 751 
>> ++++++++++++++++++++++++
>>  2 files changed, 755 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index f57458dbe763..bdea9bf4eeca 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -288,6 +288,10 @@ &qupv3_id_0 {
>>  	status = "okay";
>>  };
>> 
>> +&qupv3_id_1 {
>> +	status = "okay";
>> +};
>> +
>>  &uart5 {
>>  	status = "okay";
>>  };
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index b783f5622a66..348a34f3448e 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -881,6 +881,437 @@ uart7: serial@99c000 {
>>  			};
>>  		};
>> 
>> +		qupv3_id_1: geniqup@ac0000 {
>> +			compatible = "qcom,geni-se-qup";
>> +			reg = <0 0x00ac0000 0 0x2000>;
>> +			clock-names = "m-ahb", "s-ahb";
>> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
>> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +			iommus = <&apps_smmu 0x43 0x0>;
>> +			interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt 
>> SLAVE_QUP_CORE_1 0>;
>> +			interconnect-names = "qup-core";
> 
> We used to have interconnect votes for the wrapper, but I recently
> merged patches that dropped these for sc7180, so please conclude which
> way this should be.
> 
> The rest looks good.
> 
> Regards,
> Bjorn

Sorry, forgot to remove interconnect votes here for both the wrappers.
I will correct this in the follow up patch.

Thanks,
Roja

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
  2021-06-06  3:49   ` Bjorn Andersson
@ 2021-06-08  8:16     ` rojay
  0 siblings, 0 replies; 17+ messages in thread
From: rojay @ 2021-06-08  8:16 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On 2021-06-06 09:19, Bjorn Andersson wrote:
> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> 
>> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>> 
>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> ---
>> Changes in V3:
>>  - Broken the huge V2 patch into 3 smaller patches.
>>    1. QSPI DT nodes
>>    2. QUP wrapper_0 DT nodes
>>    3. QUP wrapper_1 DT nodes
>> 
>> Changes in V2:
>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>>  - As per Doug's comments split of SPI, UART nodes has been done.
>>  - Moved QSPI node before aps_smmu as per the order.
>> 
>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts |  97 ++-
>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 750 
>> +++++++++++++++++++++++-
>>  2 files changed, 835 insertions(+), 12 deletions(-)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> index d0edffc15736..f57458dbe763 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> @@ -292,6 +292,16 @@ &uart5 {
>>  	status = "okay";
>>  };
>> 
>> +&uart7 {
>> +	status = "okay";
>> +
>> +	/delete-property/interrupts;
>> +	interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
>> +				<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
>> +	pinctrl-names = "default", "sleep";
>> +	pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, 
>> <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
>> +};
>> +
>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>> 
>>  &qspi_cs0 {
>> @@ -307,16 +317,87 @@ &qspi_data01 {
>>  	bias-pull-up;
>>  };
>> 
>> -&qup_uart5_default {
>> -	tx {
>> -		pins = "gpio46";
> 
> Commit message says "add stuff", but somehow uart5 is no longer
> gpio46/47 and these gpios are no longer specified.
> 
> Can you roll this in a way where the giant patch actually _only_ adds
> a whole bunch of stuff?
> 
>> -		drive-strength = <2>;
>> -		bias-disable;
>> +&qup_uart5_tx {
>> +	drive-strength = <2>;
>> +	bias-disable;
>> +};
>> +
> 
> Regards,
> Bjorn


Okay, so shall I split this 2/3rd patch into two with
one patch modifying uart5 node and the other one with
_only_ adds rest all nodes?

Thanks,
Roja

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-06-08  8:07     ` rojay
@ 2021-07-06  9:19       ` rojay
  2021-07-09  0:56         ` Stephen Boyd
  0 siblings, 1 reply; 17+ messages in thread
From: rojay @ 2021-07-06  9:19 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

On 2021-06-08 13:37, rojay@codeaurora.org wrote:
> On 2021-06-06 09:25, Bjorn Andersson wrote:
>> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
>> 
>>> Add QSPI DT node for SC7280 SoC.
>>> 
>>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>>> ---
>>> Changes in V3:
>>>  - Broken the huge V2 patch into 3 smaller patches.
>>>    1. QSPI DT nodes
>>>    2. QUP wrapper_0 DT nodes
>>>    3. QUP wrapper_1 DT nodes
>>> 
>>> Changes in V2:
>>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>>>  - As per Doug's comments split of SPI, UART nodes has been done.
>>>  - Moved QSPI node before aps_smmu as per the order.
>>> 
>>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
>>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61 
>>> +++++++++++++++++++++++++
>>>  2 files changed, 90 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
>>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>>> index 3900cfc09562..d0edffc15736 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>>>  		};
>>>  };
>>> 
>>> +&qspi {
>>> +	status = "okay";
>>> +	pinctrl-names = "default";
>>> +	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>>> +
>>> +	flash@0 {
>>> +		compatible = "jedec,spi-nor";
>>> +		reg = <0>;
>>> +
>>> +		/* TODO: Increase frequency after testing */
>>> +		spi-max-frequency = <25000000>;
>>> +		spi-tx-bus-width = <2>;
>>> +		spi-rx-bus-width = <2>;
>>> +	};
>>> +};
>>> +
>>>  &qupv3_id_0 {
>>>  	status = "okay";
>>>  };
>>> @@ -278,6 +294,19 @@ &uart5 {
>>> 
>>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>>> 
>>> +&qspi_cs0 {
>>> +	bias-disable;
>>> +};
>>> +
>>> +&qspi_clk {
>>> +	bias-disable;
>>> +};
>>> +
>>> +&qspi_data01 {
>>> +	/* High-Z when no transfers; nice to park the lines */
>>> +	bias-pull-up;
>>> +};
>>> +
>>>  &qup_uart5_default {
>>>  	tx {
>>>  		pins = "gpio46";
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 6c9d5eb93f93..3047ab802cd2 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
>>>  			};
>>>  		};
>>> 
>>> +		qspi_opp_table: qspi-opp-table {
>> 
>> This node doesn't represents anything on the mmio bus, so it shouldn't
>> live in in /soc. Can't you move it into &qspi?
>> 
>> Regards,
>> Bjorn
>> 
> 
> Sure, will move it into qspi node.
> 
> Thanks,
> Roja
> 

Hi Bjorn,

Moving "qspi_opp_table" inside &qspi node causing this warning:
arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning 
(spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg 
property

Shall I keep the qspi-opp-table out of &qspi node?

Thanks,
Roja

>>> +			compatible = "operating-points-v2";
>>> +
>>> +			opp-75000000 {
>>> +				opp-hz = /bits/ 64 <75000000>;
>>> +				required-opps = <&rpmhpd_opp_low_svs>;
>>> +			};
>>> +
>>> +			opp-150000000 {
>>> +				opp-hz = /bits/ 64 <150000000>;
>>> +				required-opps = <&rpmhpd_opp_svs>;
>>> +			};
>>> +
>>> +			opp-300000000 {
>>> +				opp-hz = /bits/ 64 <300000000>;
>>> +				required-opps = <&rpmhpd_opp_nom>;
>>> +			};
>>> +		};
>>> +
>>> +		qspi: spi@88dc000 {
>>> +			compatible = "qcom,qspi-v1";
>>> +			reg = <0 0x088dc000 0 0x1000>;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <0>;
>>> +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
>>> +			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
>>> +				 <&gcc GCC_QSPI_CORE_CLK>;
>>> +			clock-names = "iface", "core";
>>> +			interconnects = <&gem_noc MASTER_APPSS_PROC 0
>>> +					&cnoc2 SLAVE_QSPI_0 0>;
>>> +			interconnect-names = "qspi-config";
>>> +			power-domains = <&rpmhpd SC7280_CX>;
>>> +			operating-points-v2 = <&qspi_opp_table>;
>>> +			status = "disabled";
>>> +		};

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-07-06  9:19       ` rojay
@ 2021-07-09  0:56         ` Stephen Boyd
  2021-07-14  7:47           ` rojay
  0 siblings, 1 reply; 17+ messages in thread
From: Stephen Boyd @ 2021-07-09  0:56 UTC (permalink / raw)
  To: Bjorn Andersson, rojay
  Cc: agross, robh+dt, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy

Quoting rojay@codeaurora.org (2021-07-06 02:19:27)
> On 2021-06-08 13:37, rojay@codeaurora.org wrote:
> > On 2021-06-06 09:25, Bjorn Andersson wrote:
> >> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> >>
> >>> Add QSPI DT node for SC7280 SoC.
> >>>
> >>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> >>> ---
> >>> Changes in V3:
> >>>  - Broken the huge V2 patch into 3 smaller patches.
> >>>    1. QSPI DT nodes
> >>>    2. QUP wrapper_0 DT nodes
> >>>    3. QUP wrapper_1 DT nodes
> >>>
> >>> Changes in V2:
> >>>  - As per Doug's comments removed pinmux/pinconf subnodes.
> >>>  - As per Doug's comments split of SPI, UART nodes has been done.
> >>>  - Moved QSPI node before aps_smmu as per the order.
> >>>
> >>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
> >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61
> >>> +++++++++++++++++++++++++
> >>>  2 files changed, 90 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> >>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> >>> index 3900cfc09562..d0edffc15736 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> >>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
> >>>             };
> >>>  };
> >>>
> >>> +&qspi {
> >>> +   status = "okay";
> >>> +   pinctrl-names = "default";
> >>> +   pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> >>> +
> >>> +   flash@0 {
> >>> +           compatible = "jedec,spi-nor";
> >>> +           reg = <0>;
> >>> +
> >>> +           /* TODO: Increase frequency after testing */
> >>> +           spi-max-frequency = <25000000>;
> >>> +           spi-tx-bus-width = <2>;
> >>> +           spi-rx-bus-width = <2>;
> >>> +   };
> >>> +};
> >>> +
> >>>  &qupv3_id_0 {
> >>>     status = "okay";
> >>>  };
> >>> @@ -278,6 +294,19 @@ &uart5 {
> >>>
> >>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
> >>>
> >>> +&qspi_cs0 {
> >>> +   bias-disable;
> >>> +};
> >>> +
> >>> +&qspi_clk {
> >>> +   bias-disable;
> >>> +};
> >>> +
> >>> +&qspi_data01 {
> >>> +   /* High-Z when no transfers; nice to park the lines */
> >>> +   bias-pull-up;
> >>> +};
> >>> +
> >>>  &qup_uart5_default {
> >>>     tx {
> >>>             pins = "gpio46";
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> index 6c9d5eb93f93..3047ab802cd2 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
> >>>                     };
> >>>             };
> >>>
> >>> +           qspi_opp_table: qspi-opp-table {
> >>
> >> This node doesn't represents anything on the mmio bus, so it shouldn't
> >> live in in /soc. Can't you move it into &qspi?
> >>
> >> Regards,
> >> Bjorn
> >>
> >
> > Sure, will move it into qspi node.
> >
> > Thanks,
> > Roja
> >
>
> Hi Bjorn,
>
> Moving "qspi_opp_table" inside &qspi node causing this warning:
> arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning
> (spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg
> property

If DT folks are OK I think we should hard-code 'opp-table' as not a
device for spi to populate on the spi bus and relax the warning in the
devicetree compiler (see [1] for more details). Technically, nodes that
are bus controllers assume all child nodes are devices on that bus.  In
this case, we want to stick the opp table as a child of the spi node so
that it can be called 'opp-table' and not be a node in the root of DT.

>
> Shall I keep the qspi-opp-table out of &qspi node?
>

If you do, please move it to / instead of putting it under /soc as it
doesn't have an address or a reg property.

[1] https://github.com/dgibson/dtc/blob/69595a167f06c4482ce784e30df1ac9b16ceb5b0/checks.c#L1844

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-07-09  0:56         ` Stephen Boyd
@ 2021-07-14  7:47           ` rojay
  2021-07-19 20:08             ` Bjorn Andersson
  0 siblings, 1 reply; 17+ messages in thread
From: rojay @ 2021-07-14  7:47 UTC (permalink / raw)
  To: Stephen Boyd, robh+dt
  Cc: Bjorn Andersson, agross, linux-arm-msm, devicetree, linux-kernel,
	Rajendra Nayak, saiprakash.ranjan, msavaliy, rajpat

On 2021-07-09 06:26, Stephen Boyd wrote:
> Quoting rojay@codeaurora.org (2021-07-06 02:19:27)
>> On 2021-06-08 13:37, rojay@codeaurora.org wrote:
>> > On 2021-06-06 09:25, Bjorn Andersson wrote:
>> >> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
>> >>
>> >>> Add QSPI DT node for SC7280 SoC.
>> >>>
>> >>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> >>> ---
>> >>> Changes in V3:
>> >>>  - Broken the huge V2 patch into 3 smaller patches.
>> >>>    1. QSPI DT nodes
>> >>>    2. QUP wrapper_0 DT nodes
>> >>>    3. QUP wrapper_1 DT nodes
>> >>>
>> >>> Changes in V2:
>> >>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>> >>>  - As per Doug's comments split of SPI, UART nodes has been done.
>> >>>  - Moved QSPI node before aps_smmu as per the order.
>> >>>
>> >>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
>> >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61
>> >>> +++++++++++++++++++++++++
>> >>>  2 files changed, 90 insertions(+)
>> >>>
>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> >>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> >>> index 3900cfc09562..d0edffc15736 100644
>> >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> >>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>> >>>             };
>> >>>  };
>> >>>
>> >>> +&qspi {
>> >>> +   status = "okay";
>> >>> +   pinctrl-names = "default";
>> >>> +   pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>> >>> +
>> >>> +   flash@0 {
>> >>> +           compatible = "jedec,spi-nor";
>> >>> +           reg = <0>;
>> >>> +
>> >>> +           /* TODO: Increase frequency after testing */
>> >>> +           spi-max-frequency = <25000000>;
>> >>> +           spi-tx-bus-width = <2>;
>> >>> +           spi-rx-bus-width = <2>;
>> >>> +   };
>> >>> +};
>> >>> +
>> >>>  &qupv3_id_0 {
>> >>>     status = "okay";
>> >>>  };
>> >>> @@ -278,6 +294,19 @@ &uart5 {
>> >>>
>> >>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>> >>>
>> >>> +&qspi_cs0 {
>> >>> +   bias-disable;
>> >>> +};
>> >>> +
>> >>> +&qspi_clk {
>> >>> +   bias-disable;
>> >>> +};
>> >>> +
>> >>> +&qspi_data01 {
>> >>> +   /* High-Z when no transfers; nice to park the lines */
>> >>> +   bias-pull-up;
>> >>> +};
>> >>> +
>> >>>  &qup_uart5_default {
>> >>>     tx {
>> >>>             pins = "gpio46";
>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> index 6c9d5eb93f93..3047ab802cd2 100644
>> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> >>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
>> >>>                     };
>> >>>             };
>> >>>
>> >>> +           qspi_opp_table: qspi-opp-table {
>> >>
>> >> This node doesn't represents anything on the mmio bus, so it shouldn't
>> >> live in in /soc. Can't you move it into &qspi?
>> >>
>> >> Regards,
>> >> Bjorn
>> >>
>> >
>> > Sure, will move it into qspi node.
>> >
>> > Thanks,
>> > Roja
>> >
>> 
>> Hi Bjorn,
>> 
>> Moving "qspi_opp_table" inside &qspi node causing this warning:
>> arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning
>> (spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg
>> property
> 
> If DT folks are OK I think we should hard-code 'opp-table' as not a
> device for spi to populate on the spi bus and relax the warning in the
> devicetree compiler (see [1] for more details). Technically, nodes that
> are bus controllers assume all child nodes are devices on that bus.  In
> this case, we want to stick the opp table as a child of the spi node so
> that it can be called 'opp-table' and not be a node in the root of DT.
> 
>> 
>> Shall I keep the qspi-opp-table out of &qspi node?
>> 
> 
> If you do, please move it to / instead of putting it under /soc as it
> doesn't have an address or a reg property.
> 

Hi Bjorn, Rob

Can we move this "qspi_opp_table" to / from /soc?

Thanks,
Roja

> [1]
> https://github.com/dgibson/dtc/blob/69595a167f06c4482ce784e30df1ac9b16ceb5b0/checks.c#L1844

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-07-14  7:47           ` rojay
@ 2021-07-19 20:08             ` Bjorn Andersson
  2021-09-09  4:43               ` rajpat
  0 siblings, 1 reply; 17+ messages in thread
From: Bjorn Andersson @ 2021-07-19 20:08 UTC (permalink / raw)
  To: rojay
  Cc: Stephen Boyd, robh+dt, agross, linux-arm-msm, devicetree,
	linux-kernel, Rajendra Nayak, saiprakash.ranjan, msavaliy,
	rajpat

On Wed 14 Jul 02:47 CDT 2021, rojay@codeaurora.org wrote:

> On 2021-07-09 06:26, Stephen Boyd wrote:
> > Quoting rojay@codeaurora.org (2021-07-06 02:19:27)
> > > On 2021-06-08 13:37, rojay@codeaurora.org wrote:
> > > > On 2021-06-06 09:25, Bjorn Andersson wrote:
> > > >> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
> > > >>
> > > >>> Add QSPI DT node for SC7280 SoC.
> > > >>>
> > > >>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> > > >>> ---
> > > >>> Changes in V3:
> > > >>>  - Broken the huge V2 patch into 3 smaller patches.
> > > >>>    1. QSPI DT nodes
> > > >>>    2. QUP wrapper_0 DT nodes
> > > >>>    3. QUP wrapper_1 DT nodes
> > > >>>
> > > >>> Changes in V2:
> > > >>>  - As per Doug's comments removed pinmux/pinconf subnodes.
> > > >>>  - As per Doug's comments split of SPI, UART nodes has been done.
> > > >>>  - Moved QSPI node before aps_smmu as per the order.
> > > >>>
> > > >>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
> > > >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61
> > > >>> +++++++++++++++++++++++++
> > > >>>  2 files changed, 90 insertions(+)
> > > >>>
> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > >>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > >>> index 3900cfc09562..d0edffc15736 100644
> > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > > >>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
> > > >>>             };
> > > >>>  };
> > > >>>
> > > >>> +&qspi {
> > > >>> +   status = "okay";
> > > >>> +   pinctrl-names = "default";
> > > >>> +   pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> > > >>> +
> > > >>> +   flash@0 {
> > > >>> +           compatible = "jedec,spi-nor";
> > > >>> +           reg = <0>;
> > > >>> +
> > > >>> +           /* TODO: Increase frequency after testing */
> > > >>> +           spi-max-frequency = <25000000>;
> > > >>> +           spi-tx-bus-width = <2>;
> > > >>> +           spi-rx-bus-width = <2>;
> > > >>> +   };
> > > >>> +};
> > > >>> +
> > > >>>  &qupv3_id_0 {
> > > >>>     status = "okay";
> > > >>>  };
> > > >>> @@ -278,6 +294,19 @@ &uart5 {
> > > >>>
> > > >>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
> > > >>>
> > > >>> +&qspi_cs0 {
> > > >>> +   bias-disable;
> > > >>> +};
> > > >>> +
> > > >>> +&qspi_clk {
> > > >>> +   bias-disable;
> > > >>> +};
> > > >>> +
> > > >>> +&qspi_data01 {
> > > >>> +   /* High-Z when no transfers; nice to park the lines */
> > > >>> +   bias-pull-up;
> > > >>> +};
> > > >>> +
> > > >>>  &qup_uart5_default {
> > > >>>     tx {
> > > >>>             pins = "gpio46";
> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > >>> index 6c9d5eb93f93..3047ab802cd2 100644
> > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > > >>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
> > > >>>                     };
> > > >>>             };
> > > >>>
> > > >>> +           qspi_opp_table: qspi-opp-table {
> > > >>
> > > >> This node doesn't represents anything on the mmio bus, so it shouldn't
> > > >> live in in /soc. Can't you move it into &qspi?
> > > >>
> > > >> Regards,
> > > >> Bjorn
> > > >>
> > > >
> > > > Sure, will move it into qspi node.
> > > >
> > > > Thanks,
> > > > Roja
> > > >
> > > 
> > > Hi Bjorn,
> > > 
> > > Moving "qspi_opp_table" inside &qspi node causing this warning:
> > > arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning
> > > (spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg
> > > property
> > 
> > If DT folks are OK I think we should hard-code 'opp-table' as not a
> > device for spi to populate on the spi bus and relax the warning in the
> > devicetree compiler (see [1] for more details). Technically, nodes that
> > are bus controllers assume all child nodes are devices on that bus.  In
> > this case, we want to stick the opp table as a child of the spi node so
> > that it can be called 'opp-table' and not be a node in the root of DT.
> > 
> > > 
> > > Shall I keep the qspi-opp-table out of &qspi node?
> > > 
> > 
> > If you do, please move it to / instead of putting it under /soc as it
> > doesn't have an address or a reg property.
> > 
> 
> Hi Bjorn, Rob
> 
> Can we move this "qspi_opp_table" to / from /soc?
> 

If you have made a proper attempt to convince Rob and Mark that
a child "opp-table" in a SPI master is not a SPI device - and the
conclusion is that this is not a good idea...then yes it should live
outside /soc.

Thanks,
Bjorn

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node
  2021-07-19 20:08             ` Bjorn Andersson
@ 2021-09-09  4:43               ` rajpat
  0 siblings, 0 replies; 17+ messages in thread
From: rajpat @ 2021-09-09  4:43 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: Stephen Boyd, robh+dt, agross, linux-arm-msm, devicetree,
	linux-kernel, Rajendra Nayak, saiprakash.ranjan, msavaliy, mka,
	dianders

On 2021-07-20 01:38, Bjorn Andersson wrote:
> On Wed 14 Jul 02:47 CDT 2021, rojay@codeaurora.org wrote:
> 
>> On 2021-07-09 06:26, Stephen Boyd wrote:
>> > Quoting rojay@codeaurora.org (2021-07-06 02:19:27)
>> > > On 2021-06-08 13:37, rojay@codeaurora.org wrote:
>> > > > On 2021-06-06 09:25, Bjorn Andersson wrote:
>> > > >> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
>> > > >>
>> > > >>> Add QSPI DT node for SC7280 SoC.
>> > > >>>
>> > > >>> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
>> > > >>> ---
>> > > >>> Changes in V3:
>> > > >>>  - Broken the huge V2 patch into 3 smaller patches.
>> > > >>>    1. QSPI DT nodes
>> > > >>>    2. QUP wrapper_0 DT nodes
>> > > >>>    3. QUP wrapper_1 DT nodes
>> > > >>>
>> > > >>> Changes in V2:
>> > > >>>  - As per Doug's comments removed pinmux/pinconf subnodes.
>> > > >>>  - As per Doug's comments split of SPI, UART nodes has been done.
>> > > >>>  - Moved QSPI node before aps_smmu as per the order.
>> > > >>>
>> > > >>>  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
>> > > >>>  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61
>> > > >>> +++++++++++++++++++++++++
>> > > >>>  2 files changed, 90 insertions(+)
>> > > >>>
>> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > >>> b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > >>> index 3900cfc09562..d0edffc15736 100644
>> > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
>> > > >>> @@ -268,6 +268,22 @@ pmr735b_die_temp {
>> > > >>>             };
>> > > >>>  };
>> > > >>>
>> > > >>> +&qspi {
>> > > >>> +   status = "okay";
>> > > >>> +   pinctrl-names = "default";
>> > > >>> +   pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
>> > > >>> +
>> > > >>> +   flash@0 {
>> > > >>> +           compatible = "jedec,spi-nor";
>> > > >>> +           reg = <0>;
>> > > >>> +
>> > > >>> +           /* TODO: Increase frequency after testing */
>> > > >>> +           spi-max-frequency = <25000000>;
>> > > >>> +           spi-tx-bus-width = <2>;
>> > > >>> +           spi-rx-bus-width = <2>;
>> > > >>> +   };
>> > > >>> +};
>> > > >>> +
>> > > >>>  &qupv3_id_0 {
>> > > >>>     status = "okay";
>> > > >>>  };
>> > > >>> @@ -278,6 +294,19 @@ &uart5 {
>> > > >>>
>> > > >>>  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
>> > > >>>
>> > > >>> +&qspi_cs0 {
>> > > >>> +   bias-disable;
>> > > >>> +};
>> > > >>> +
>> > > >>> +&qspi_clk {
>> > > >>> +   bias-disable;
>> > > >>> +};
>> > > >>> +
>> > > >>> +&qspi_data01 {
>> > > >>> +   /* High-Z when no transfers; nice to park the lines */
>> > > >>> +   bias-pull-up;
>> > > >>> +};
>> > > >>> +
>> > > >>>  &qup_uart5_default {
>> > > >>>     tx {
>> > > >>>             pins = "gpio46";
>> > > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > >>> index 6c9d5eb93f93..3047ab802cd2 100644
>> > > >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> > > >>> @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
>> > > >>>                     };
>> > > >>>             };
>> > > >>>
>> > > >>> +           qspi_opp_table: qspi-opp-table {
>> > > >>
>> > > >> This node doesn't represents anything on the mmio bus, so it shouldn't
>> > > >> live in in /soc. Can't you move it into &qspi?
>> > > >>
>> > > >> Regards,
>> > > >> Bjorn
>> > > >>
>> > > >
>> > > > Sure, will move it into qspi node.
>> > > >
>> > > > Thanks,
>> > > > Roja
>> > > >
>> > >
>> > > Hi Bjorn,
>> > >
>> > > Moving "qspi_opp_table" inside &qspi node causing this warning:
>> > > arch/arm64/boot/dts/qcom/sc7280.dtsi:1055.35-1072.6: Warning
>> > > (spi_bus_reg): /soc@0/spi@88dc000/qspi-opp-table: missing or empty reg
>> > > property
>> >
>> > If DT folks are OK I think we should hard-code 'opp-table' as not a
>> > device for spi to populate on the spi bus and relax the warning in the
>> > devicetree compiler (see [1] for more details). Technically, nodes that
>> > are bus controllers assume all child nodes are devices on that bus.  In
>> > this case, we want to stick the opp table as a child of the spi node so
>> > that it can be called 'opp-table' and not be a node in the root of DT.
>> >
>> > >
>> > > Shall I keep the qspi-opp-table out of &qspi node?
>> > >
>> >
>> > If you do, please move it to / instead of putting it under /soc as it
>> > doesn't have an address or a reg property.
>> >
>> 
>> Hi Bjorn, Rob
>> 
>> Can we move this "qspi_opp_table" to / from /soc?
>> 
> 
> If you have made a proper attempt to convince Rob and Mark that
> a child "opp-table" in a SPI master is not a SPI device - and the
> conclusion is that this is not a good idea...then yes it should live
> outside /soc.
> 
> Thanks,
> Bjorn

Hi Rob/Mark,

adding "qspi_opp_table" inside &qspi node causing warning
we are getting "empty reg warning". qspi_opp_table contain
frequencies for qspi and i think putting "opp-table" under qspi node is 
not a
good idea because if we put under qspi it will treat "opp-table" as a 
device on the bus.
in this scenario "opp-table" is not a device on the bus. so we moved 
qspi_opp_table from /soc to /.
please give your inputs about this.

Thanks and Regards,
Rajesh

^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2021-09-09  4:44 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-04 13:54 [PATCH V3 0/3] Add QSPI and QUPv3 DT nodes for SC7280 SoC Roja Rani Yarubandi
2021-06-04 13:54 ` [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node Roja Rani Yarubandi
2021-06-04 21:45   ` Stephen Boyd
2021-06-08  8:05     ` rojay
2021-06-06  3:55   ` Bjorn Andersson
2021-06-08  8:07     ` rojay
2021-07-06  9:19       ` rojay
2021-07-09  0:56         ` Stephen Boyd
2021-07-14  7:47           ` rojay
2021-07-19 20:08             ` Bjorn Andersson
2021-09-09  4:43               ` rajpat
2021-06-04 13:54 ` [PATCH V3 2/3] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Roja Rani Yarubandi
2021-06-06  3:49   ` Bjorn Andersson
2021-06-08  8:16     ` rojay
2021-06-04 13:54 ` [PATCH V3 3/3] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Roja Rani Yarubandi
2021-06-06  3:53   ` Bjorn Andersson
2021-06-08  8:10     ` rojay

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