From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07B29C48BDF for ; Thu, 10 Jun 2021 21:44:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E3A8F61404 for ; Thu, 10 Jun 2021 21:44:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230322AbhFJVq0 (ORCPT ); Thu, 10 Jun 2021 17:46:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229941AbhFJVqY (ORCPT ); Thu, 10 Jun 2021 17:46:24 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1421EC061574; Thu, 10 Jun 2021 14:44:16 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id v13so1750453ple.9; Thu, 10 Jun 2021 14:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=klF+qD/QdtC30F6g+izrwAUhrIJ7PWDhzmkE9PFXPQI=; b=ExKWQpdm/J1verQNW9M8RVGytkUTQoT+Aw/Bbyg5wznaZE/onMVQiSFtgfoEJCNqct 8hpHcUOID8+2VhXl47OZOH1CF84ugny9gUpSnFpo5eom37wwejVKV3PWuyTHSaXPNrBs qheJWd+O4Yz86u6UXGmY99RroGEx1ewlSUye7iEH0Hh8kJxUZFPBtRorZz7U0R7DsKcd UVrDTlOmi56/5d5rvUGdo1hHXUyfHW3o2TtrESOQijmCb+qz+FgvUAH+3QVgnplIpJzF 5kIc8F2GJU8PprFiA4yrtKykcviA6NPbgyCW8933zQb6Rx9wQPi3QRkC/nZGQNlW96/U NyJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=klF+qD/QdtC30F6g+izrwAUhrIJ7PWDhzmkE9PFXPQI=; b=GK5V6nj6nCd4y77ryrsW+N9WDRVppvwCyBZzrWOSMuqcZV7ffu1LD3NBuHeyBfCPw/ 7warVhVrSEtlCfimeG85tDW0/Ea9KcnuOCnC1IgNoXWlT+uCXryTMepKRRIYiGJDPGQ3 GTsiBzPiXroC/gVdAX3+GkTdgIbWVZutddJYFZHRI5XZlbfYBDonLF8en3Iyjau8Qxnf ZyLgxxHtZSKjS+RRF+vY00inWwrnmnV2HsJP4G3l+cwELRbfUP9pQ8Zb/dgwh5O3X/J9 RGYIA2qxbEru+jrnrYOXKwLK9qWfvddnWvp//mGSmmagWOHHddT+5x54Pnx6wd1XRGQG xmnQ== X-Gm-Message-State: AOAM5324Q6q+OMzwRLnqHO8SojYrnb1JFc7fQTzGLQIHoKx3Ts6W3oZe gU8O5jPNMm+SUf/xDnVwubUwoXdcmIB+8g== X-Google-Smtp-Source: ABdhPJzctNcqGZbrqPW8mgLIzRunvhAu6QFEKdLYF1YOfvfPDINI4s4OTD3IppMH7l326xKSJS7w1A== X-Received: by 2002:a17:902:724c:b029:ef:571f:8894 with SMTP id c12-20020a170902724cb02900ef571f8894mr734948pll.49.1623361455583; Thu, 10 Jun 2021 14:44:15 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id b14sm3426369pgl.52.2021.06.10.14.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jun 2021 14:44:14 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Jordan Crouse , Jordan Crouse , Rob Clark , Rob Clark , Sean Paul , David Airlie , Daniel Vetter , AngeloGioacchino Del Regno , Konrad Dybcio , "Kristian H. Kristensen" , Marijn Suijten , Jonathan Marek , Akhil P Oommen , Sai Prakash Ranjan , Eric Anholt , Sharat Masetty , Douglas Anderson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 3/5] drm/msm: Improve the a6xx page fault handler Date: Thu, 10 Jun 2021 14:44:11 -0700 Message-Id: <20210610214431.539029-4-robdclark@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210610214431.539029-1-robdclark@gmail.com> References: <20210610214431.539029-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jordan Crouse Use the new adreno-smmu-priv fault info function to get more SMMU debug registers and print the current TTBR0 to debug per-instance pagetables and figure out which GPU block generated the request. Signed-off-by: Jordan Crouse Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 76 +++++++++++++++++++++++++-- drivers/gpu/drm/msm/msm_iommu.c | 11 +++- drivers/gpu/drm/msm/msm_mmu.h | 4 +- 4 files changed, 87 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f46562c12022..eb030b00bff4 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1075,7 +1075,7 @@ bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return true; } -static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) +static int a5xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg; pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", @@ -1085,7 +1085,7 @@ static int a5xx_fault_handler(void *arg, unsigned long iova, int flags) gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7))); - return -EFAULT; + return 0; } static void a5xx_cp_err_irq(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c7f0ddb12d8f..fc19db10bff1 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1032,18 +1032,88 @@ static void a6xx_recover(struct msm_gpu *gpu) msm_gpu_hw_init(gpu); } -static int a6xx_fault_handler(void *arg, unsigned long iova, int flags) +static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) +{ + static const char *uche_clients[7] = { + "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", + }; + u32 val; + + if (mid < 1 || mid > 3) + return "UNKNOWN"; + + /* + * The source of the data depends on the mid ID read from FSYNR1. + * and the client ID read from the UCHE block + */ + val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); + + /* mid = 3 is most precise and refers to only one block per client */ + if (mid == 3) + return uche_clients[val & 7]; + + /* For mid=2 the source is TP or VFD except when the client id is 0 */ + if (mid == 2) + return ((val & 7) == 0) ? "TP" : "TP|VFD"; + + /* For mid=1 just return "UCHE" as a catchall for everything else */ + return "UCHE"; +} + +static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) +{ + if (id == 0) + return "CP"; + else if (id == 4) + return "CCU"; + else if (id == 6) + return "CDP Prefetch"; + + return a6xx_uche_fault_block(gpu, id); +} + +#define ARM_SMMU_FSR_TF BIT(1) +#define ARM_SMMU_FSR_PF BIT(3) +#define ARM_SMMU_FSR_EF BIT(4) + +static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data) { struct msm_gpu *gpu = arg; + struct adreno_smmu_fault_info *info = data; + const char *type = "UNKNOWN"; - pr_warn_ratelimited("*** gpu fault: iova=%08lx, flags=%d (%u,%u,%u,%u)\n", + /* + * Print a default message if we couldn't get the data from the + * adreno-smmu-priv + */ + if (!info) { + pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n", iova, flags, gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); - return -EFAULT; + return 0; + } + + if (info->fsr & ARM_SMMU_FSR_TF) + type = "TRANSLATION"; + else if (info->fsr & ARM_SMMU_FSR_PF) + type = "PERMISSION"; + else if (info->fsr & ARM_SMMU_FSR_EF) + type = "EXTERNAL"; + + pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n", + info->ttbr0, iova, + flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ", type, + a6xx_fault_block(gpu, info->fsynr1 & 0xff), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7))); + + return 0; } static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 50d881794758..6975b95c3c29 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -211,8 +211,17 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { struct msm_iommu *iommu = arg; + struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(iommu->base.dev); + struct adreno_smmu_fault_info info, *ptr = NULL; + + if (adreno_smmu->get_fault_info) { + adreno_smmu->get_fault_info(adreno_smmu->cookie, &info); + ptr = &info; + } + if (iommu->base.handler) - return iommu->base.handler(iommu->base.arg, iova, flags); + return iommu->base.handler(iommu->base.arg, iova, flags, ptr); + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); return 0; } diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index 61ade89d9e48..a88f44c3268d 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -26,7 +26,7 @@ enum msm_mmu_type { struct msm_mmu { const struct msm_mmu_funcs *funcs; struct device *dev; - int (*handler)(void *arg, unsigned long iova, int flags); + int (*handler)(void *arg, unsigned long iova, int flags, void *data); void *arg; enum msm_mmu_type type; }; @@ -43,7 +43,7 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, - int (*handler)(void *arg, unsigned long iova, int flags)) + int (*handler)(void *arg, unsigned long iova, int flags, void *data)) { mmu->arg = arg; mmu->handler = handler; -- 2.31.1