From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A4F5C49EA5 for ; Mon, 21 Jun 2021 16:17:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7717361206 for ; Mon, 21 Jun 2021 16:17:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230490AbhFUQTO (ORCPT ); Mon, 21 Jun 2021 12:19:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230202AbhFUQTM (ORCPT ); Mon, 21 Jun 2021 12:19:12 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D859C061756 for ; Mon, 21 Jun 2021 09:16:58 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id a127so3487812pfa.10 for ; Mon, 21 Jun 2021 09:16:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RTHZO4ku4j5vDvD/bzt1UBNEgDqw9PSCh2QcJgfEprc=; b=xRbg6j4kh1I6iFqd35sh2Ji+qOCOySFPrihg0LzUvR2WU8l2qcc4J4V4Nss0y7Y3uY y2Q82B1ij+6s8QYIbGu5iFXv2MXEnJM++xON+qdtKlVzSWQzNuAlvbaQHncWU6/Kn1rb Ee8RGzJd6+Hh6/Xe0ntM0Wu/rzUnyXtBTr6tt7yaycQRLz658p5AonwH2xvR8G5y0TZe HwvzyDEuvv8UPdqLVDmVKKIzqTjKkgyMFOIaFZPIf7KoRyKGvH1T39sc96YTQU1Rsi3F kkzcxcKjRBZtGlpzI3hRnuYrtNEELAf+GkXYyIF9GGAwbkjUeaBtE7XVIw02/ciCpF1i abGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RTHZO4ku4j5vDvD/bzt1UBNEgDqw9PSCh2QcJgfEprc=; b=ZXQ3gHfCfEOAiHYtYe6AfElIeGSabTpsM3awRomDnlk4STbGyM3k5Vi8ug7opVxQY5 9+dVIbJkDkUPQa6xEPI6GkZT6Wt+ZZnhJKu1nO1L+5qTIp4AQCAzdPH75tDGAAPZaZ2r g7tsCli5KywFXT5iDoGPQ+d+A1s1XjDzWoIniX00kgCs24TP7f8hUYIS3DKuBUP6+3Ve MWzP1Y5Lyfpug64+A077H61kQL1ve6G1sd5FMGGAGMG6IzJVNFubcp0BAZYoapgjVa1a fXAgZaX77J4gySGboTBr+0CjMplrNQuPA+gVVh70v1Z3gJTnNQksvXv6PpoSfNid5zRb EpMQ== X-Gm-Message-State: AOAM531n3TfIGTQctpLALqs3e1G9BCIEnv9LicUQphCkeIRDr6QNqp5e Kc4vK5lQCgkKabg8XW/pdPQP X-Google-Smtp-Source: ABdhPJxnr/WIssHOkCiZeDEBk6anAvL2NAZ51kSkowrVMOXl188MRtbROX8L2MwOUYkqc/2MPHZj+Q== X-Received: by 2002:a05:6a00:1983:b029:2fe:bc09:3042 with SMTP id d3-20020a056a001983b02902febc093042mr20630098pfl.72.1624292217533; Mon, 21 Jun 2021 09:16:57 -0700 (PDT) Received: from localhost.localdomain ([120.138.13.116]) by smtp.gmail.com with ESMTPSA id k88sm10734730pjk.15.2021.06.21.09.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Jun 2021 09:16:56 -0700 (PDT) From: Manivannan Sadhasivam To: gregkh@linuxfoundation.org Cc: hemantk@codeaurora.org, bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, loic.poulain@linaro.org, stable@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 7/8] bus: mhi: pci_generic: Apply no-op for wake using sideband wake boolean Date: Mon, 21 Jun 2021 21:46:15 +0530 Message-Id: <20210621161616.77524-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621161616.77524-1-manivannan.sadhasivam@linaro.org> References: <20210621161616.77524-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bhaumik Bhatt Devices such as SDX24 do not have the provision for inband wake doorbell in the form of channel 127 and instead have a sideband GPIO for it. Newer devices such as SDX55 or SDX65 support inband wake method by default. Ensure the functionality is used based on this such that device wake stays held when a client driver uses mhi_device_get() API or the equivalent debugfs entry. Cc: stable@vger.kernel.org Fixes: e3e5e6508fc1 ("bus: mhi: pci_generic: No-Op for device_wake operations") Signed-off-by: Bhaumik Bhatt Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1624053302-22470-1-git-send-email-bbhatt@codeaurora.org Signed-off-by: Manivannan Sadhasivam --- drivers/bus/mhi/pci_generic.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index d84b74396c6a..eb9263bd1bd8 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -32,6 +32,8 @@ * @edl: emergency download mode firmware path (if any) * @bar_num: PCI base address register to use for MHI MMIO register space * @dma_data_width: DMA transfer word size (32 or 64 bits) + * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead + * of inband wake support (such as sdx24) */ struct mhi_pci_dev_info { const struct mhi_controller_config *config; @@ -40,6 +42,7 @@ struct mhi_pci_dev_info { const char *edl; unsigned int bar_num; unsigned int dma_data_width; + bool sideband_wake; }; #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ @@ -242,7 +245,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { .edl = "qcom/sdx65m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { @@ -251,7 +255,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { @@ -259,7 +264,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_qcom_v1_mhiv_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true }; static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { @@ -301,7 +307,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { .edl = "qcom/prog_firehose_sdx24.mbn", .config = &modem_quectel_em1xx_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = true }; static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { @@ -339,7 +346,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { .edl = "qcom/sdx55m/edl.mbn", .config = &modem_foxconn_sdx55_config, .bar_num = MHI_PCI_DEFAULT_BAR_NUM, - .dma_data_width = 32 + .dma_data_width = 32, + .sideband_wake = false }; static const struct pci_device_id mhi_pci_id_table[] = { @@ -640,9 +648,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) mhi_cntrl->status_cb = mhi_pci_status_cb; mhi_cntrl->runtime_get = mhi_pci_runtime_get; mhi_cntrl->runtime_put = mhi_pci_runtime_put; - mhi_cntrl->wake_get = mhi_pci_wake_get_nop; - mhi_cntrl->wake_put = mhi_pci_wake_put_nop; - mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + + if (info->sideband_wake) { + mhi_cntrl->wake_get = mhi_pci_wake_get_nop; + mhi_cntrl->wake_put = mhi_pci_wake_put_nop; + mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; + } err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); if (err) -- 2.25.1