[PATCH v1 0/5] Add rpmcc and rpmpd for SM4250/6115

[PATCH v1 0/5] Add rpmcc and rpmpd for SM4250/6115

[Iskren Chernev]

This patch adds support for the RPM clocks and power domains on QCom SM4250 and
SM6115, codename bengal. The rpmcc code is converted from downstream code
(OnePlus repo [1]), and the rpmpd is converted from downstream DT extracted
from OnePlus Nord N100.

The downstream code has additional voter clocks, which let consumers vote and
the driver to select the highest desired clock rate for a given (real) parent
clock [2]. I might port that as well in the near future, let me know if there
is a more elegant solution.

[1]: https://github.com/OnePlusOSS/android_kernel_oneplus_sm4250
[2]: https://source.codeaurora.org/quic/server/kernel/commit/?h=v4.9.137&id=6a4951a8308c5729ae8e502787cb705477c94251

Iskren Chernev (5):
  dt-bindings: soc: qcom: smd-rpm: Add SM4250,6115 compatible
  dt-bindings: clock: qcom: rpmcc: Document SM6115,SM4250 compatible
  clk: qcom: smd: Add support for SM6115 rpm clocks
  dt-bindings: power: rpmpd: Add SM4250,SM6115 to rpmpd binding
  drivers: soc: qcom: rpmpd: Add SM6115 RPM Power Domains

 .../devicetree/bindings/clock/qcom,rpmcc.txt  |  2 +
 .../devicetree/bindings/power/qcom,rpmpd.yaml |  2 +
 .../bindings/soc/qcom/qcom,smd-rpm.yaml       |  2 +
 drivers/clk/qcom/clk-smd-rpm.c                | 64 +++++++++++++++++++
 drivers/soc/qcom/rpmpd.c                      | 29 +++++++++
 drivers/soc/qcom/smd-rpm.c                    |  2 +
 include/dt-bindings/clock/qcom,rpmcc.h        | 10 +++
 include/dt-bindings/power/qcom-rpmpd.h        | 20 ++++++
 include/linux/soc/qcom/smd-rpm.h              |  1 +
 9 files changed, 132 insertions(+)


base-commit: e71e3a48a7e89fa71fb70bf4602367528864d2ff
-- 
2.31.1

[PATCH v1 1/5] dt-bindings: soc: qcom: smd-rpm: Add SM4250,6115 compatible

[Iskren Chernev]

Add the dt-binding for the rpm on the Qualcomm SM4250 and SM6115 SoC
platform.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
 Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
index d511f01fcac6..d9e97d8bc738 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -39,6 +39,8 @@ properties:
       - qcom,rpm-msm8996
       - qcom,rpm-msm8998
       - qcom,rpm-sdm660
+      - qcom,rpm-sm4250
+      - qcom,rpm-sm6115
       - qcom,rpm-sm6125
       - qcom,rpm-qcs404
 
-- 
2.31.1

[PATCH v1 2/5] dt-bindings: clock: qcom: rpmcc: Document SM6115,SM4250 compatible

[Iskren Chernev]

Add the dt-binding for the RPM Clock Controller on the SM6115 and SM4250
SoC.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt |  2 ++
 include/dt-bindings/clock/qcom,rpmcc.h                 | 10 ++++++++++
 2 files changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 6cf5a7ec2b4c..869d73cb29b8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -25,6 +25,8 @@ Required properties :
 			"qcom,rpmcc-msm8998", "qcom,rpmcc"
 			"qcom,rpmcc-qcs404", "qcom,rpmcc"
 			"qcom,rpmcc-sdm660", "qcom,rpmcc"
+			"qcom,rpmcc-sm4250", "qcom,rpmcc"
+			"qcom,rpmcc-sm6115", "qcom,rpmcc"
 
 - #clock-cells : shall contain 1
 
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 8aaba7cd9589..aa834d516234 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -149,5 +149,15 @@
 #define RPM_SMD_CE2_A_CLK			103
 #define RPM_SMD_CE3_CLK				104
 #define RPM_SMD_CE3_A_CLK			105
+#define RPM_SMD_QUP_CLK				106
+#define RPM_SMD_QUP_A_CLK			107
+#define RPM_SMD_MMRT_CLK			108
+#define RPM_SMD_MMRT_A_CLK			109
+#define RPM_SMD_MMNRT_CLK			110
+#define RPM_SMD_MMNRT_A_CLK			111
+#define RPM_SMD_SNOC_PERIPH_CLK			112
+#define RPM_SMD_SNOC_PERIPH_A_CLK		113
+#define RPM_SMD_SNOC_LPASS_CLK			114
+#define RPM_SMD_SNOC_LPASS_A_CLK		115
 
 #endif
-- 
2.31.1

[PATCH v1 3/5] clk: qcom: smd: Add support for SM6115 rpm clocks

[Iskren Chernev]

Add rpm smd clocks, PMIC and bus clocks which are required on
SM4250/SM6115 for clients to vote on.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
 drivers/clk/qcom/clk-smd-rpm.c   | 64 ++++++++++++++++++++++++++++++++
 drivers/soc/qcom/smd-rpm.c       |  2 +
 include/linux/soc/qcom/smd-rpm.h |  1 +
 3 files changed, 67 insertions(+)

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index daf09dd61055..2c9de650bb63 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -913,6 +913,68 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 	.num_clks = ARRAY_SIZE(sdm660_clks),
 };
 
+/* sm6115 */
+DEFINE_CLK_SMD_RPM_BRANCH(sm6115, bi_tcxo, bi_tcxo_ao,
+					QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
+DEFINE_CLK_SMD_RPM(sm6115, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(sm6115, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM_BRANCH(sm6115, qdss_clk, qdss_a_clk,
+					QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
+DEFINE_CLK_SMD_RPM(sm6115, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
+DEFINE_CLK_SMD_RPM(sm6115, snoc_periph_clk, snoc_periph_a_clk,
+						QCOM_SMD_RPM_BUS_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6115, snoc_lpass_clk, snoc_lpass_a_clk,
+						QCOM_SMD_RPM_BUS_CLK, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk1, rf_clk1_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(sm6115, rf_clk2, rf_clk2_a, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk1_pin, rf_clk1_a_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sm6115, rf_clk2_pin, rf_clk2_a_pin, 5);
+
+static struct clk_smd_rpm *sm6115_clks[] = {
+	[RPM_SMD_XO_CLK_SRC] = &sm6115_bi_tcxo,
+	[RPM_SMD_XO_A_CLK_SRC] = &sm6115_bi_tcxo_ao,
+	[RPM_SMD_SNOC_CLK] = &sm6115_snoc_clk,
+	[RPM_SMD_SNOC_A_CLK] = &sm6115_snoc_a_clk,
+	[RPM_SMD_BIMC_CLK] = &sm6115_bimc_clk,
+	[RPM_SMD_BIMC_A_CLK] = &sm6115_bimc_a_clk,
+	[RPM_SMD_QDSS_CLK] = &sm6115_qdss_clk,
+	[RPM_SMD_QDSS_A_CLK] = &sm6115_qdss_a_clk,
+	[RPM_SMD_RF_CLK1] = &sm6115_rf_clk1,
+	[RPM_SMD_RF_CLK1_A] = &sm6115_rf_clk1_a,
+	[RPM_SMD_RF_CLK2] = &sm6115_rf_clk2,
+	[RPM_SMD_RF_CLK2_A] = &sm6115_rf_clk2_a,
+	[RPM_SMD_CNOC_CLK] = &sm6115_cnoc_clk,
+	[RPM_SMD_CNOC_A_CLK] = &sm6115_cnoc_a_clk,
+	[RPM_SMD_IPA_CLK] = &sm6115_ipa_clk,
+	[RPM_SMD_IPA_A_CLK] = &sm6115_ipa_a_clk,
+	[RPM_SMD_QUP_CLK] = &sm6115_qup_clk,
+	[RPM_SMD_QUP_A_CLK] = &sm6115_qup_a_clk,
+	[RPM_SMD_MMRT_CLK] = &sm6115_mmrt_clk,
+	[RPM_SMD_MMRT_A_CLK] = &sm6115_mmrt_a_clk,
+	[RPM_SMD_MMNRT_CLK] = &sm6115_mmnrt_clk,
+	[RPM_SMD_MMNRT_A_CLK] = &sm6115_mmnrt_a_clk,
+	[RPM_SMD_SNOC_PERIPH_CLK] = &sm6115_snoc_periph_clk,
+	[RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6115_snoc_periph_a_clk,
+	[RPM_SMD_SNOC_LPASS_CLK] = &sm6115_snoc_lpass_clk,
+	[RPM_SMD_SNOC_LPASS_A_CLK] = &sm6115_snoc_lpass_a_clk,
+	[RPM_SMD_CE1_CLK] = &sm6115_ce1_clk,
+	[RPM_SMD_CE1_A_CLK] = &sm6115_ce1_a_clk,
+	[RPM_SMD_RF_CLK1_PIN] = &sm6115_rf_clk1_pin,
+	[RPM_SMD_RF_CLK1_A_PIN] = &sm6115_rf_clk1_a_pin,
+	[RPM_SMD_RF_CLK2_PIN] = &sm6115_rf_clk2_pin,
+	[RPM_SMD_RF_CLK2_A_PIN] = &sm6115_rf_clk2_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
+	.clks = sm6115_clks,
+	.num_clks = ARRAY_SIZE(sm6115_clks),
+};
+
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
 	{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
@@ -924,6 +986,8 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
 	{ .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
 	{ .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
+	{ .compatible = "qcom,rpmcc-sm4250",  .data = &rpm_clk_sm6115  },
+	{ .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c
index bc0be1d4be5f..83c844892643 100644
--- a/drivers/soc/qcom/smd-rpm.c
+++ b/drivers/soc/qcom/smd-rpm.c
@@ -242,6 +242,8 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = {
 	{ .compatible = "qcom,rpm-msm8996" },
 	{ .compatible = "qcom,rpm-msm8998" },
 	{ .compatible = "qcom,rpm-sdm660" },
+	{ .compatible = "qcom,rpm-sm4250" },
+	{ .compatible = "qcom,rpm-sm6115" },
 	{ .compatible = "qcom,rpm-sm6125" },
 	{ .compatible = "qcom,rpm-qcs404" },
 	{}
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index f2645ec52520..d350685039ad 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -37,6 +37,7 @@ struct qcom_smd_rpm;
 #define QCOM_SMD_RPM_IPA_CLK	0x617069
 #define QCOM_SMD_RPM_CE_CLK	0x6563
 #define QCOM_SMD_RPM_AGGR_CLK	0x72676761
+#define QCOM_SMD_RPM_QUP_CLK    0x00707571
 
 int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
 		       int state,
-- 
2.31.1

[PATCH v1 4/5] dt-bindings: power: rpmpd: Add SM4250,SM6115 to rpmpd binding

[Iskren Chernev]

Add compatible and constants for the power domains exposed by the RPM
in the Qualcomm SM4250 and SM6115 platforms.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
 .../devicetree/bindings/power/qcom,rpmpd.yaml |  2 ++
 include/dt-bindings/power/qcom-rpmpd.h        | 20 +++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
index 4807b560f00d..4deffbbf54d0 100644
--- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
@@ -30,6 +30,8 @@ properties:
       - qcom,sc8180x-rpmhpd
       - qcom,sdm845-rpmhpd
       - qcom,sdx55-rpmhpd
+      - qcom,sm4250-rpmpd
+      - qcom,sm6115-rpmpd
       - qcom,sm8150-rpmhpd
       - qcom,sm8250-rpmhpd
       - qcom,sm8350-rpmhpd
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index 8b5708bb9671..5917fb7e7b7b 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -192,6 +192,26 @@
 #define SDM660_SSCMX		8
 #define SDM660_SSCMX_VFL	9
 
+/* SM4250 Power Domains */
+#define SM4250_VDDCX		0
+#define SM4250_VDDCX_AO		1
+#define SM4250_VDDCX_VFL	2
+#define SM4250_VDDMX		3
+#define SM4250_VDDMX_AO		4
+#define SM4250_VDDMX_VFL	5
+#define SM4250_VDD_LPI_CX	6
+#define SM4250_VDD_LPI_MX	7
+
+/* SM6115 Power Domains */
+#define SM6115_VDDCX		0
+#define SM6115_VDDCX_AO		1
+#define SM6115_VDDCX_VFL	2
+#define SM6115_VDDMX		3
+#define SM6115_VDDMX_AO		4
+#define SM6115_VDDMX_VFL	5
+#define SM6115_VDD_LPI_CX	6
+#define SM6115_VDD_LPI_MX	7
+
 /* RPM SMD Power Domain performance levels */
 #define RPM_SMD_LEVEL_RETENTION       16
 #define RPM_SMD_LEVEL_RETENTION_PLUS  32
-- 
2.31.1

[PATCH v1 5/5] drivers: soc: qcom: rpmpd: Add SM6115 RPM Power Domains

[Iskren Chernev]

The SM6115 (and the compatible SM4250) have 4 rpm power domains, ported
from downstream DT.

Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
---
 drivers/soc/qcom/rpmpd.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c
index 0b532a892d60..290b2f9db4e4 100644
--- a/drivers/soc/qcom/rpmpd.c
+++ b/drivers/soc/qcom/rpmpd.c
@@ -346,6 +346,33 @@ static const struct rpmpd_desc sdm660_desc = {
 	.max_state = RPM_SMD_LEVEL_TURBO,
 };
 
+/* sm6115 and sm4250 RPM Power domains */
+DEFINE_RPMPD_PAIR(sm6115, vddcx, vddcx_ao, RWCX, LEVEL, 0);
+DEFINE_RPMPD_VFL(sm6115, vddcx_vfl, RWCX, 0);
+
+DEFINE_RPMPD_PAIR(sm6115, vddmx, vddmx_ao, RWMX, LEVEL, 0);
+DEFINE_RPMPD_VFL(sm6115, vddmx_vfl, RWMX, 0);
+
+DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_cx, RWLC, 0);
+DEFINE_RPMPD_LEVEL(sm6115, vdd_lpi_mx, RWLM, 0);
+
+static struct rpmpd *sm6115_rpmpds[] = {
+	[SM6115_VDDCX] =		&sm6115_vddcx,
+	[SM6115_VDDCX_AO] =		&sm6115_vddcx_ao,
+	[SM6115_VDDCX_VFL] =		&sm6115_vddcx_vfl,
+	[SM6115_VDDMX] =		&sm6115_vddmx,
+	[SM6115_VDDMX_AO] =		&sm6115_vddmx_ao,
+	[SM6115_VDDMX_VFL] =		&sm6115_vddmx_vfl,
+	[SM6115_VDD_LPI_CX] =		&sm6115_vdd_lpi_cx,
+	[SM6115_VDD_LPI_MX] =		&sm6115_vdd_lpi_mx,
+};
+
+static const struct rpmpd_desc sm6115_desc = {
+	.rpmpds = sm6115_rpmpds,
+	.num_pds = ARRAY_SIZE(sm6115_rpmpds),
+	.max_state = RPM_SMD_LEVEL_TURBO_NO_CPR,
+};
+
 static const struct of_device_id rpmpd_match_table[] = {
 	{ .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc },
 	{ .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc },
@@ -356,6 +383,8 @@ static const struct of_device_id rpmpd_match_table[] = {
 	{ .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc },
 	{ .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc },
 	{ .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc },
+	{ .compatible = "qcom,sm4250-rpmpd", .data = &sm6115_desc },
+	{ .compatible = "qcom,sm6115-rpmpd", .data = &sm6115_desc },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpmpd_match_table);
-- 
2.31.1

Re: [PATCH v1 1/5] dt-bindings: soc: qcom: smd-rpm: Add SM4250,6115 compatible

[Rob Herring]

On Tue, 22 Jun 2021 23:21:52 +0300, Iskren Chernev wrote:
> Add the dt-binding for the rpm on the Qualcomm SM4250 and SM6115 SoC
> platform.
> 
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
>  Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v1 2/5] dt-bindings: clock: qcom: rpmcc: Document SM6115,SM4250 compatible

[Rob Herring]

On Tue, 22 Jun 2021 23:21:53 +0300, Iskren Chernev wrote:
> Add the dt-binding for the RPM Clock Controller on the SM6115 and SM4250
> SoC.
> 
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/qcom,rpmcc.txt |  2 ++
>  include/dt-bindings/clock/qcom,rpmcc.h                 | 10 ++++++++++
>  2 files changed, 12 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v1 4/5] dt-bindings: power: rpmpd: Add SM4250,SM6115 to rpmpd binding

[Rob Herring]

On Tue, 22 Jun 2021 23:21:55 +0300, Iskren Chernev wrote:
> Add compatible and constants for the power domains exposed by the RPM
> in the Qualcomm SM4250 and SM6115 platforms.
> 
> Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
> ---
>  .../devicetree/bindings/power/qcom,rpmpd.yaml |  2 ++
>  include/dt-bindings/power/qcom-rpmpd.h        | 20 +++++++++++++++++++
>  2 files changed, 22 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>