From: Thara Gopinath <thara.gopinath@linaro.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
rui.zhang@intel.com, daniel.lezcano@linaro.org,
viresh.kumar@linaro.org, rjw@rjwysocki.net, robh+dt@kernel.org
Cc: steev@kali.org, linux-arm-msm@vger.kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [Patch v4 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh
Date: Tue, 27 Jul 2021 11:25:12 -0400 [thread overview]
Message-ID: <20210727152512.1098329-7-thara.gopinath@linaro.org> (raw)
In-Reply-To: <20210727152512.1098329-1-thara.gopinath@linaro.org>
Add dt binding documentation to describe Qualcomm
Limits Management Hardware node.
Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
v3->v4:
- Changed dt property qcom,lmh-cpu-id to qcom,lmh-cpu and made it
a phandle pointing to the cpu node instead of a number as per
Rob Herring's review comments.
- Added suffix -millicelsius to all temperature properties as per
Rob Herring's review comments.
- Dropped unnecessary #includes in the example as pointed out by Bjorn.
- Other minor fixes.
.../devicetree/bindings/thermal/qcom-lmh.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
new file mode 100644
index 000000000000..0978f458b9ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Limits Management Hardware(LMh)
+
+maintainers:
+ - Thara Gopinath <thara.gopinath@linaro.org>
+
+description:
+ Limits Management Hardware(LMh) is a hardware infrastructure on some
+ Qualcomm SoCs that can enforce temperature and current limits as
+ programmed by software for certain IPs like CPU.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-lmh
+
+ reg:
+ items:
+ - description: core registers
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ qcom,lmh-cpu:
+ description:
+ phandle of the first cpu in the LMh cluster
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ qcom,lmh-temp-arm-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the LMh thermal
+ FSM is engaged.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ qcom,lmh-temp-low-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to remove frequency throttling.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ qcom,lmh-temp-high-millicelsius:
+ description:
+ An integer expressing temperature threshold at which the state machine
+ will attempt to throttle the frequency.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - #interrupt-cells
+ - interrupt-controller
+ - qcom,lmh-cpu
+ - qcom,lmh-temp-arm-millicelsius
+ - qcom,lmh-temp-low-millicelsius
+ - qcom,lmh-temp-high-millicelsius
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0x17d70800 0x401>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0x17d78800 0x401>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu = <&CPU0>;
+ qcom,lmh-temp-arm-millicelsius = <65000>;
+ qcom,lmh-temp-low-millicelsius = <94500>;
+ qcom,lmh-temp-high-millicelsius = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ - |
--
2.25.1
next prev parent reply other threads:[~2021-07-27 15:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-27 15:25 [Patch v4 0/6] Introduce LMh driver for Qualcomm SoCs Thara Gopinath
2021-07-27 15:25 ` [Patch v4 1/6] firmware: qcom_scm: Introduce SCM calls to access LMh Thara Gopinath
2021-07-27 15:25 ` [Patch v4 2/6] thermal: qcom: Add support for LMh driver Thara Gopinath
2021-07-27 15:25 ` [Patch v4 3/6] cpufreq: qcom-cpufreq-hw: Add dcvs interrupt support Thara Gopinath
2021-07-28 3:50 ` Viresh Kumar
2021-07-28 22:19 ` Thara Gopinath
2021-07-29 6:17 ` Viresh Kumar
2021-07-29 11:13 ` Thara Gopinath
2021-07-29 11:15 ` Viresh Kumar
2021-07-27 15:25 ` [Patch v4 4/6] arm64: dts: qcom: sdm45: Add support for LMh node Thara Gopinath
2021-07-27 15:25 ` [Patch v4 5/6] arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones Thara Gopinath
2021-07-27 15:25 ` Thara Gopinath [this message]
2021-07-27 18:26 ` [Patch v4 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh Rob Herring
2021-07-28 16:10 ` Rob Herring
2021-08-02 21:29 ` Thara Gopinath
2021-07-27 17:44 ` [Patch v4 0/6] Introduce LMh driver for Qualcomm SoCs Steev Klimaszewski
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210727152512.1098329-7-thara.gopinath@linaro.org \
--to=thara.gopinath@linaro.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rjw@rjwysocki.net \
--cc=robh+dt@kernel.org \
--cc=rui.zhang@intel.com \
--cc=steev@kali.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).