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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@somainline.org>
To: bjorn.andersson@linaro.org
Cc: agross@kernel.org, robh+dt@kernel.org, lgirdwood@gmail.com,
	broonie@kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	phone-devel@vger.kernel.org, konrad.dybcio@somainline.org,
	marijn.suijten@somainline.org, jami.kettunen@somainline.org,
	paul.bouchara@somainline.org, martin.botka@somainline.org,
	~postmarketos/upstreaming@lists.sr.ht, jeffrey.l.hugo@gmail.com,
	robh@kernel.org,
	AngeloGioacchino Del Regno 
	<angelogioacchino.delregno@somainline.org>
Subject: [PATCH v7 3/6] arm64: qcom: qcs404: Change CPR nvmem-names
Date: Wed,  1 Sep 2021 17:57:32 +0200	[thread overview]
Message-ID: <20210901155735.629282-4-angelogioacchino.delregno@somainline.org> (raw)
In-Reply-To: <20210901155735.629282-1-angelogioacchino.delregno@somainline.org>

The CPR driver's common functions were split and put in another
file in order to support newer CPR revisions: to simplify the
commonization, the expected names of the fuses had to be changed
in order for both new and old support to use the same fuse name
retrieval function and keeping the naming consistent.

The thread id was added to the fuse name and, since CPRv1 does
not support threads, it is expected to always read ID 0, which
means that the expected name here is now "cpr0_(fuse_name)"
instead of "cpr_(fuse_name)": luckily, QCS404 is the only user
so change it accordingly.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 339790ba585d..23e70f473da4 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1168,18 +1168,18 @@ cpr: power-controller@b018000 {
 				<&cpr_efuse_ring2>,
 				<&cpr_efuse_ring3>,
 				<&cpr_efuse_revision>;
-			nvmem-cell-names = "cpr_quotient_offset1",
-				"cpr_quotient_offset2",
-				"cpr_quotient_offset3",
-				"cpr_init_voltage1",
-				"cpr_init_voltage2",
-				"cpr_init_voltage3",
-				"cpr_quotient1",
-				"cpr_quotient2",
-				"cpr_quotient3",
-				"cpr_ring_osc1",
-				"cpr_ring_osc2",
-				"cpr_ring_osc3",
+			nvmem-cell-names = "cpr0_quotient_offset1",
+				"cpr0_quotient_offset2",
+				"cpr0_quotient_offset3",
+				"cpr0_init_voltage1",
+				"cpr0_init_voltage2",
+				"cpr0_init_voltage3",
+				"cpr0_quotient1",
+				"cpr0_quotient2",
+				"cpr0_quotient3",
+				"cpr0_ring_osc1",
+				"cpr0_ring_osc2",
+				"cpr0_ring_osc3",
 				"cpr_fuse_revision";
 		};
 
-- 
2.32.0


  parent reply	other threads:[~2021-09-01 15:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-01 15:57 [PATCH v7 0/6] Add support for Core Power Reduction v3, v4 and Hardened AngeloGioacchino Del Regno
2021-09-01 15:57 ` [PATCH v7 1/6] soc: qcom: cpr: Move common functions to new file AngeloGioacchino Del Regno
2021-10-15 11:15   ` Vladimir Zapolskiy
2021-09-01 15:57 ` [PATCH v7 2/6] dt-bindings: avs: cpr: Convert binding to YAML schema AngeloGioacchino Del Regno
2021-09-07 18:28   ` Rob Herring
2021-09-20  0:51   ` Bjorn Andersson
2021-09-01 15:57 ` AngeloGioacchino Del Regno [this message]
2021-09-01 15:57 ` [PATCH v7 4/6] soc: qcom: Add support for Core Power Reduction v3, v4 and Hardened AngeloGioacchino Del Regno
2021-09-01 15:57 ` [PATCH v7 5/6] MAINTAINERS: Add entry for Qualcomm CPRv3/v4/Hardened driver AngeloGioacchino Del Regno
2021-09-01 15:57 ` [PATCH v7 6/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver AngeloGioacchino Del Regno

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