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Thu, 21 Oct 2021 00:36:52 -0700 (PDT) Received: from workstation ([202.21.43.20]) by smtp.gmail.com with ESMTPSA id x31sm4832983pfu.40.2021.10.21.00.36.49 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Oct 2021 00:36:51 -0700 (PDT) Date: Thu, 21 Oct 2021 13:06:47 +0530 From: Manivannan Sadhasivam To: Prasad Malisetty Cc: svarbanov@mm-sol.com, agross@kernel.org, bjorn.andersson@linaro.org, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, vbadigan@codeaurora.org, kw@linux.com, bhelgaas@google.com Subject: Re: [PATCH v1] PCI: qcom: Fix incorrect register offset in pcie init Message-ID: <20211021073647.GA7580@workstation> References: <1634237929-25459-1-git-send-email-pmaliset@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1634237929-25459-1-git-send-email-pmaliset@codeaurora.org> User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri, Oct 15, 2021 at 12:28:49AM +0530, Prasad Malisetty wrote: > In pcie_init_2_7_0 one of the register writes using incorrect offset > as per the platform register definitions (PCIE_PARF_AXI_MSTR_WR_ADDR_HALT > offset value should be 0x1A8 instead 0x178). > Update the correct offset value for SDM845 platform. > > fixes: ed8cc3b1 ("PCI: qcom: Add support for SDM845 PCIe controller") > > Signed-off-by: Prasad Malisetty After incorporating the reviews from Bjorn H, Reviewed-by: Manivannan Sadhasivam Thanks, Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 8a7a300..5bce152 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1230,9 +1230,9 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > > if (IS_ENABLED(CONFIG_PCI_MSI)) { > - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > val |= BIT(31); > - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); > + writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); > } > > return 0; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >