From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Subject: [PATCH v1 04/10] PCI: qcom: do not duplicate qcom_pcie_cfg fields in qcom_pcie struct
Date: Thu, 2 Dec 2021 17:17:20 +0300 [thread overview]
Message-ID: <20211202141726.1796793-5-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20211202141726.1796793-1-dmitry.baryshkov@linaro.org>
In preparation to adding more flags to configuration data, use struct
qcom_pcie_cfg directly inside struct qcom_pcie, rather than duplicating
all its fields. This would save us from the boilerplate code that just
copies flags values from one sruct to another one.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 34 ++++++++++++--------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 3bee901c4df7..64f762cdbc7d 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -204,8 +204,7 @@ struct qcom_pcie {
union qcom_pcie_resources res;
struct phy *phy;
struct gpio_desc *reset;
- const struct qcom_pcie_ops *ops;
- unsigned int pipe_clk_need_muxing:1;
+ struct qcom_pcie_cfg cfg;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -229,8 +228,8 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
struct qcom_pcie *pcie = to_qcom_pcie(pci);
/* Enable Link Training state machine */
- if (pcie->ops->ltssm_enable)
- pcie->ops->ltssm_enable(pcie);
+ if (pcie->cfg.ops->ltssm_enable)
+ pcie->cfg.ops->ltssm_enable(pcie);
return 0;
}
@@ -1176,7 +1175,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
- if (pcie->pipe_clk_need_muxing) {
+ if (pcie->cfg.pipe_clk_need_muxing) {
res->pipe_clk_src = devm_clk_get(dev, "pipe_mux");
if (IS_ERR(res->pipe_clk_src))
return PTR_ERR(res->pipe_clk_src);
@@ -1209,7 +1208,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
}
/* Set TCXO as clock source for pcie_pipe_clk_src */
- if (pcie->pipe_clk_need_muxing)
+ if (pcie->cfg.pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->ref_clk_src);
ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
@@ -1287,7 +1286,7 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
/* Set pipe clock as clock source for pcie_pipe_clk_src */
- if (pcie->pipe_clk_need_muxing)
+ if (pcie->cfg.pipe_clk_need_muxing)
clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk);
return clk_prepare_enable(res->pipe_clk);
@@ -1387,7 +1386,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
- ret = pcie->ops->init(pcie);
+ ret = pcie->cfg.ops->init(pcie);
if (ret)
return ret;
@@ -1395,16 +1394,16 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
if (ret)
goto err_deinit;
- if (pcie->ops->post_init) {
- ret = pcie->ops->post_init(pcie);
+ if (pcie->cfg.ops->post_init) {
+ ret = pcie->cfg.ops->post_init(pcie);
if (ret)
goto err_disable_phy;
}
qcom_ep_reset_deassert(pcie);
- if (pcie->ops->config_sid) {
- ret = pcie->ops->config_sid(pcie);
+ if (pcie->cfg.ops->config_sid) {
+ ret = pcie->cfg.ops->config_sid(pcie);
if (ret)
goto err;
}
@@ -1413,12 +1412,12 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
err:
qcom_ep_reset_assert(pcie);
- if (pcie->ops->post_deinit)
- pcie->ops->post_deinit(pcie);
+ if (pcie->cfg.ops->post_deinit)
+ pcie->cfg.ops->post_deinit(pcie);
err_disable_phy:
phy_power_off(pcie->phy);
err_deinit:
- pcie->ops->deinit(pcie);
+ pcie->cfg.ops->deinit(pcie);
return ret;
}
@@ -1562,8 +1561,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
return -EINVAL;
}
- pcie->ops = pcie_cfg->ops;
- pcie->pipe_clk_need_muxing = pcie_cfg->pipe_clk_need_muxing;
+ pcie->cfg = *pcie_cfg;
pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
if (IS_ERR(pcie->reset)) {
@@ -1589,7 +1587,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
- ret = pcie->ops->get_resources(pcie);
+ ret = pcie->cfg.ops->get_resources(pcie);
if (ret)
goto err_pm_runtime_put;
--
2.33.0
next prev parent reply other threads:[~2021-12-02 14:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 14:17 [PATCH v1 00/10] qcom: add support for PCIe0 on SM8450 platform Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 01/10] dt-bindings: pci: qcom: Document PCIe bindings for SM8450 Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 02/10] dt-bindings: phy: qcom,qmp: Add SM8450 PCIe PHY bindings Dmitry Baryshkov
2021-12-07 14:26 ` Bjorn Andersson
2021-12-02 14:17 ` [PATCH v1 03/10] phy: qcom-qmp: Add SM8450 PCIe0 PHY support Dmitry Baryshkov
2021-12-07 14:30 ` Bjorn Andersson
2021-12-02 14:17 ` Dmitry Baryshkov [this message]
2021-12-06 19:59 ` [PATCH v1 04/10] PCI: qcom: do not duplicate qcom_pcie_cfg fields in qcom_pcie struct Bjorn Helgaas
2021-12-02 14:17 ` [PATCH v1 05/10] PCI: qcom: add flag to enable use of ddrss_sf_tbu clock Dmitry Baryshkov
2021-12-06 19:53 ` Bjorn Helgaas
2021-12-02 14:17 ` [PATCH v1 06/10] PCI: qcom: add support for SM8450 PCIe controllers Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 08/10] arm64: dts: qcom: sm8450: add PCIe0 root device Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 09/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Dmitry Baryshkov
2021-12-02 14:17 ` [PATCH v1 10/10] arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Dmitry Baryshkov
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