From: Stephen Boyd <sboyd@kernel.org>
To: agross@kernel.org, bjorn.andersson@linaro.org, maz@kernel.org,
mturquette@baylibre.com, quic_vamslank@quicinc.com,
robh+dt@kernel.org, tglx@linutronix.de
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
manivannan.sadhasivam@linaro.org,
Vamsi Krishna Lanka <quic_vamslank@quicinc.com>,
Vinod Koul <vkoul@kernel.org>
Subject: Re: [PATCH v6 2/5] clk: qcom: Add LUCID_EVO PLL type for SDX65
Date: Thu, 02 Dec 2021 16:18:43 -0800 [thread overview]
Message-ID: <20211203001844.78E7FC00446@smtp.kernel.org> (raw)
In-Reply-To: <7e1805ef3f7cddc1222906d8b8e5b79548b46f63.1638402361.git.quic_vamslank@quicinc.com>
Quoting quic_vamslank@quicinc.com (2021-12-01 16:21:32)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index eaedcceb766f..e0c67b76d8ac 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1741,35 +1760,47 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
> LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
> }
>
> +static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate, unsigned long enable_vote_run)
> +{
> + struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
> + struct regmap *regmap = pll->clkr.regmap;
What's going on with the tabbing here?
> + int i, val = 0, div, ret;
Do we need to initialize to 0?
> + u32 mask;
> +
> + /*
> + * If the PLL is in FSM mode, then treat set_rate callback as a
> + * no-operation.
> + */
> + ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
> + if (ret)
> + return ret;
> +
> + if (val & enable_vote_run)
> + return 0;
> +
> + if (!pll->post_div_table) {
> + pr_err("Missing the post_div_table for the PLL\n");
Probably useful to know which PLL is missing a table here.
next prev parent reply other threads:[~2021-12-03 0:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 0:21 [PATCH v6 0/5] Add GCC and RPMh clock support for SDX65 quic_vamslank
2021-12-02 0:21 ` [PATCH v6 1/5] dt-bindings: clock: Add SDX65 GCC clock bindings quic_vamslank
2021-12-02 0:21 ` [PATCH v6 2/5] clk: qcom: Add LUCID_EVO PLL type for SDX65 quic_vamslank
2021-12-03 0:18 ` Stephen Boyd [this message]
2021-12-07 4:35 ` Vamsi Krishna Lanka
2021-12-02 0:21 ` [PATCH v6 3/5] clk: qcom: Add SDX65 GCC support quic_vamslank
2021-12-03 0:20 ` Stephen Boyd
2021-12-07 4:31 ` Vamsi Krishna Lanka
2021-12-02 0:21 ` [PATCH v6 4/5] dt-bindings: clock: Introduce RPMHCC bindings for SDX65 quic_vamslank
2021-12-06 22:30 ` (subset) " Bjorn Andersson
2021-12-02 0:21 ` [PATCH v6 5/5] clk: qcom: Add support for SDX65 RPMh clocks quic_vamslank
2021-12-03 16:23 ` Bjorn Andersson
2021-12-06 22:30 ` (subset) " Bjorn Andersson
2021-12-06 22:30 ` (subset) [PATCH v6 0/5] Add GCC and RPMh clock support for SDX65 Bjorn Andersson
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