From: Shawn Guo <shawn.guo@linaro.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Maulik Shah <quic_mkshah@quicinc.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Loic Poulain <loic.poulain@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/3] irqchip: Add Qualcomm MPM controller driver
Date: Tue, 7 Dec 2021 17:48:36 +0800 [thread overview]
Message-ID: <20211207094835.GO10105@dragon> (raw)
In-Reply-To: <87wnkh26ar.wl-maz@kernel.org>
On Mon, Dec 06, 2021 at 01:48:12PM +0000, Marc Zyngier wrote:
> > > > +static int qcom_mpm_enter_sleep(struct qcom_mpm_priv *priv)
> > > > +{
> > > > + int i, ret;
> > > > +
> > > > + for (i = 0; i < priv->reg_stride; i++)
> > > > + qcom_mpm_write(priv, MPM_REG_STATUS, i, 0);
> > > > +
> > > > + /* Notify RPM to write vMPM into HW */
> > >
> > > What do you mean by 'into HW'? We just did that, right? or are these
> > > registers just fake and most of the stuff is in the RPM?
> >
> > I have a note about this in commit log.
> >
> > - All the register settings are done by APSS on an internal memory
> > region called vMPM, and RPM will flush them into hardware after it
> > receives a mailbox/IPC notification from APSS.
> >
> > So yes, these registers are fake/virtual in memory, and RPM will
> > actually flush the values into the MPM hardware block.
>
> Then why are you using MMIO accessors all over the place if this is
> just RAM? Who *owns* this memory? Is it normal DRAM? Or some flops
> exposed by a device? Why isn't the state simply communicated over the
> mailbox instead?
It's a piece of internal memory (SRAM) which can be access by AP and
RPM. The communication mechanism is defined by SoC/RPM design, and we
can do nothing but following the procedure.
Shawn
next prev parent reply other threads:[~2021-12-07 9:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-02 12:21 [PATCH v3 0/3] Add Qualcomm MPM irqchip driver support Shawn Guo
2021-12-02 12:21 ` [PATCH v3 1/3] irqchip: Pass platform_device pointer to init_cb Shawn Guo
2021-12-02 17:52 ` Florian Fainelli
2021-12-02 19:10 ` Marc Zyngier
2021-12-02 21:44 ` Florian Fainelli
2021-12-06 6:40 ` Shawn Guo
2021-12-06 8:29 ` Marc Zyngier
2021-12-06 6:35 ` Shawn Guo
2021-12-02 12:21 ` [PATCH v3 2/3] dt-bindings: interrupt-controller: Add Qualcomm MPM support Shawn Guo
2021-12-02 12:21 ` [PATCH v3 3/3] irqchip: Add Qualcomm MPM controller driver Shawn Guo
2021-12-03 0:00 ` kernel test robot
2021-12-06 9:46 ` Marc Zyngier
2021-12-06 13:15 ` Shawn Guo
2021-12-06 13:48 ` Marc Zyngier
2021-12-07 9:48 ` Shawn Guo [this message]
2021-12-07 10:16 ` Marc Zyngier
2021-12-08 10:04 ` Shawn Guo
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