From: Marijn Suijten <marijn.suijten@somainline.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Taniya Das <tdas@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data
Date: Thu, 9 Dec 2021 00:11:57 +0100 [thread overview]
Message-ID: <20211208231157.cuhzstalr6woldwz@SoMainline.org> (raw)
In-Reply-To: <20211208175430.1333594-7-dmitry.baryshkov@linaro.org>
On 2021-12-08 20:54:25, Dmitry Baryshkov wrote:
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
> drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++----------------
> 1 file changed, 79 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> index 3c15e551419f..e2b4804695f3 100644
> --- a/drivers/clk/qcom/camcc-sc7180.c
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = {
> .div = 2,
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_pll2_out_early",
> - .parent_names = (const char *[]){ "cam_cc_pll2" },
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_pll2.clkr.hw,
> + },
> .num_parents = 1,
> .ops = &clk_fixed_factor_ops,
> },
> @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
> .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cam_cc_pll2_out_aux",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_pll2.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_pll2.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_bps_ahb_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_slow_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_bps_areg_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_fast_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_bps_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_bps_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_bps_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_cci_0_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cci_0_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cci_0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_cci_1_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cci_1_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cci_1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_core_ahb_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_slow_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_cpas_ahb_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_slow_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csi0phytimer_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_csi0phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csi1phytimer_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_csi1phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csi2phytimer_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_csi2phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csi3phytimer_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_csi3phytimer_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csiphy0_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csiphy1_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csiphy2_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_csiphy3_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_icp_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_icp_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_icp_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_0_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_0_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_0_cphy_rx_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_0_csid_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_0_csid_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_0_dsp_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_0_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_1_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_1_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_1_cphy_rx_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_1_csid_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_1_csid_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_1_dsp_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_1_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_lite_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_lite_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_lite_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_lite_cphy_rx_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_cphy_rx_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ife_lite_csid_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ife_lite_csid_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ipe_0_ahb_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_slow_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ipe_0_areg_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_fast_ahb_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_ipe_0_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_ipe_0_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_ipe_0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_jpeg_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_jpeg_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_jpeg_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_lrme_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_lrme_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_lrme_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_mclk0_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_mclk0_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_mclk0_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_mclk1_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_mclk1_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_mclk1_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_mclk2_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_mclk2_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_mclk2_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_mclk3_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_mclk3_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_mclk3_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
> .enable_mask = BIT(0),
> .hw.init = &(struct clk_init_data){
> .name = "cam_cc_mclk4_clk",
> - .parent_data = &(const struct clk_parent_data){
> - .hw = &cam_cc_mclk4_clk_src.clkr.hw,
> + .parent_hws = (const struct clk_hw*[]){
> + &cam_cc_mclk4_clk_src.clkr.hw,
> },
> .num_parents = 1,
> .flags = CLK_SET_RATE_PARENT,
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-12-08 23:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-08 17:54 [PATCH 00/11] clk: qcom: another round of clock drivers cleanup Dmitry Baryshkov
2021-12-08 17:54 ` [PATCH 01/11] clk: qcom: gpucc-sdm660: get rid of the test clock Dmitry Baryshkov
2021-12-09 8:08 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 02/11] clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data Dmitry Baryshkov
2021-12-08 22:44 ` Marijn Suijten
2021-12-09 8:08 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 03/11] clk: qcom: camcc-sc7180: get rid of the test clock Dmitry Baryshkov
2021-12-08 22:48 ` Marijn Suijten
2021-12-09 8:09 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 04/11] clk: qcom: camcc-sdm845: " Dmitry Baryshkov
2021-12-09 8:09 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 05/11] clk: qcom: camcc-sdm845: convert to parent data Dmitry Baryshkov
2021-12-08 23:19 ` Marijn Suijten
2021-12-08 17:54 ` [PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data Dmitry Baryshkov
2021-12-08 23:11 ` Marijn Suijten [this message]
2021-12-09 8:11 ` Stephen Boyd
2021-12-15 0:12 ` Dmitry Baryshkov
2021-12-08 17:54 ` [PATCH 07/11] clk: qcom: videocc-sc7180: " Dmitry Baryshkov
2021-12-08 22:53 ` Marijn Suijten
2021-12-09 8:11 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 08/11] clk: qcom: gcc-msm8996: drop unsupported clock sources Dmitry Baryshkov
2021-12-08 23:23 ` Marijn Suijten
2021-12-08 17:54 ` [PATCH 09/11] clk: qcom: gcc-msm8996: move clock parent tables down Dmitry Baryshkov
2021-12-08 23:11 ` Marijn Suijten
2021-12-09 8:12 ` Stephen Boyd
2021-12-08 17:54 ` [PATCH 10/11] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2021-12-08 23:09 ` Marijn Suijten
2021-12-13 23:44 ` Bjorn Andersson
2021-12-14 15:00 ` Marijn Suijten
2021-12-08 17:54 ` [PATCH 11/11] clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2021-12-08 22:54 ` Marijn Suijten
2021-12-09 8:14 ` Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211208231157.cuhzstalr6woldwz@SoMainline.org \
--to=marijn.suijten@somainline.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=dmitry.baryshkov@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=sboyd@kernel.org \
--cc=tdas@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).