From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E528EC433EF for ; Wed, 11 May 2022 08:03:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241805AbiEKIDW (ORCPT ); Wed, 11 May 2022 04:03:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243298AbiEKIDV (ORCPT ); Wed, 11 May 2022 04:03:21 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7AA48CCCF; Wed, 11 May 2022 01:03:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1652256192; x=1683792192; h=from:to:cc:subject:date:message-id; bh=U5JVmxHUUjxAbxSb6PLM4Nc67GW9UY1orKH/4MwbuNA=; b=bCkL1ocYAlLpkbyLN7JZv7gxV/tX0Dq/om1qCxl7BVVBvDJJVxPaBlZP NiawT2Qeaot9x461XiMuOIb7Vu7A/gjBPy77+vpCwZcKMjDqVejCuVN/v K7DECh5413qPPHPQRyjJGcOeQ+inm46sApQ00A/a/NR3/0bOX5S2jL/ii w=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 May 2022 01:03:10 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 May 2022 01:03:09 -0700 X-QCInternal: smtphost Received: from blr-ubuntu-435.qualcomm.com ([10.79.42.176]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 May 2022 13:32:51 +0530 Received: by blr-ubuntu-435.qualcomm.com (Postfix, from userid 2327845) id B31489008AA; Wed, 11 May 2022 13:32:50 +0530 (IST) From: Shreyas K K To: Will Deacon , Catalin Marinas , Marc Zyngier , Suzuki K Poulose , Mark Rutland Cc: Andre Przywara , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Jeffrey Hugo , Shreyas K K , Sai Prakash Ranjan , Rajendra Nayak , Prasanna Kumar Subject: [PATCH] arm64: Enable repeat tlbi workaround on KRYO4XX gold CPUs Date: Wed, 11 May 2022 13:32:47 +0530 Message-Id: <20220511080247.1530-1-quic_shrekk@quicinc.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add KRYO4XX gold/big cores to the list of CPUs that need the repeat TLBI workaround. Apply this to the affected KRYO4XX cores (rcpe to rdpe). The variant and revision bits are implementation defined and are different from the their Cortex CPU counterparts on which they are based on, i.e., (r0p0 to r1p0) is equivalent to (rcpe to rdpe). Signed-off-by: Shreyas K K --- Documentation/arm64/silicon-errata.rst | 3 +++ arch/arm64/kernel/cpu_errata.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 466cb9e89047..d27db84d585e 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -189,6 +189,9 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 | +----------------+-----------------+-----------------+-----------------------------+ +| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 | ++----------------+-----------------+-----------------+-----------------------------+ + +----------------+-----------------+-----------------+-----------------------------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 4c9b5b4b7a0b..2518657e6de1 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -208,6 +208,8 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { #ifdef CONFIG_ARM64_ERRATUM_1286807 { ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0), + /* Kryo4xx Gold (rcpe to rdpe) => (r0p0 to r1p0) */ + ERRATA_MIDR_RANGE(QCOM_CPU_PART_KRYO_4XX_GOLD, 0xc, 0xe, 0xd, 0xe), }, #endif {}, -- 2.17.1