From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15DBEC4321E for ; Thu, 12 May 2022 10:46:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352783AbiELKqS (ORCPT ); Thu, 12 May 2022 06:46:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352808AbiELKp7 (ORCPT ); Thu, 12 May 2022 06:45:59 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B57065B4 for ; Thu, 12 May 2022 03:45:51 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id h29so8335609lfj.2 for ; Thu, 12 May 2022 03:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3wF9YjekVvBPStMNtaaCYjUE+D1MeDx6T+Vgrs7ULxM=; b=PTURU6LD1Dd/2fC0HgsiAqIybmcPY6A4vl/FAOMBGMdi3EtzdDKl6VGMxaZHj/nQcw xLc/UW1bcxmrvkA9oEGi4WKJ8tdt9laI11pQeQU6NZBWb6ZmsnXkjEn6H/ceuFs0OTv5 lOA2jW2uV/JoSfpZhN8ymZlq7TRW2mt5rMpPiX+NRLlpFYAPVxyn2wo9qND/UTyuGZ3c vfLpoeu6tYH0C5hBYdU+hxEa4f7CKqQ/zv5kn81TEtt/zbdqakOjH5PC4tDZCO+JdXm0 gP6jiXO2GV1XC9CWIZD0AMdET+akmVAt42joN3WonomyW3m7eTiTsRs41Hy2aGl9Az+f bS1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wF9YjekVvBPStMNtaaCYjUE+D1MeDx6T+Vgrs7ULxM=; b=E9n3T/DC8N271qp1A0MxWpGhnpX1YEko/38W/Izi3ANmxgpI7SknzIiB0eNLSrMtg5 zuZj4LM6P3nC2tJtqp6Ca4Xk2Io04w1zisayb+XhMx4MzcnbZzVWNz66XgaY5OypcUSj J54hdoslaP5E2zLMpCqFYYYHj4wehC/Dbw/MqRmiGZqG7LVa8j5IQcbTT65uI9KW45zr Rh5iLyjUSylOvMTidiCPAH55UDQooSrMYNEqlW60g2IdzjCa0L/d3w9I7TC9c7UAONXs oJpLBX0dxwQKiFnMtRg9V53kLOcfJ07t+zPt0A14HttwVPYCnC40CEHqYKVlTxvOMFha WA1Q== X-Gm-Message-State: AOAM532G79pvD65Gnzzdonh2m9Xl8yvg6KdcATgWIk44u6vGC2mpSqir Izby8Qya6borD3HpUA5NCC+2pw== X-Google-Smtp-Source: ABdhPJwM88XVMOaQoSLikx5hnEIB5r1T5RsQHlc0QWhLeZWw2GbojxDDTRAGB4OuEI/ZZpOpxl2rSg== X-Received: by 2002:a05:6512:3184:b0:472:6042:7c2b with SMTP id i4-20020a056512318400b0047260427c2bmr24294977lfe.606.1652352350302; Thu, 12 May 2022 03:45:50 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q21-20020a2e9695000000b0024f3d1daeafsm831660lji.55.2022.05.12.03.45.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 03:45:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v8 05/10] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Date: Thu, 12 May 2022 13:45:40 +0300 Message-Id: <20220512104545.2204523-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> References: <20220512104545.2204523-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split handling of MSI host IRQs to a separate dw_pcie_msi_host_init() function. The code is complex enough to warrant a separte function. Adding another bit to support multiple host MSI IRQs would make it overcomplicated. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 97 +++++++++++-------- 1 file changed, 55 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 5f6590929319..6b0c7b75391f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -288,6 +288,59 @@ static void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } +static int dw_pcie_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct platform_device *pdev = to_platform_device(pci->dev); + int ret; + u32 ctrl, num_ctrls; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + pp->irq_mask[ctrl] = ~0; + + if (!pp->msi_irq[0]) { + int irq = platform_get_irq_byname_optional(pdev, "msi"); + + if (irq < 0) { + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + } + pp->msi_irq[0] = irq; + } + + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + for (ctrl = 0; ctrl < num_ctrls; ctrl++) + if (pp->msi_irq[ctrl] > 0) + irq_set_chained_handler_and_data(pp->msi_irq[ctrl], + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data: %d\n", ret); + pp->msi_data = 0; + dw_pcie_free_msi(pp); + return ret; + } + + return 0; +} + int dw_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -365,49 +418,9 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; } else if (pp->has_msi_ctrl) { - u32 ctrl, num_ctrls; - - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - pp->irq_mask[ctrl] = ~0; - - if (!pp->msi_irq[0]) { - int irq = platform_get_irq_byname_optional(pdev, "msi"); - - if (irq < 0) { - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - } - pp->msi_irq[0] = irq; - } - - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_msi_host_init(pp); + if (ret < 0) return ret; - - for (ctrl = 0; ctrl < num_ctrls; ctrl++) - if (pp->msi_irq[ctrl] > 0) - irq_set_chained_handler_and_data(pp->msi_irq[ctrl], - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - ret = dma_mapping_error(pci->dev, pp->msi_data); - if (ret) { - dev_err(pci->dev, "Failed to map MSI data: %d\n", ret); - pp->msi_data = 0; - goto err_free_msi; - } } } -- 2.35.1