* [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
@ 2022-10-06 14:45 Krzysztof Kozlowski
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-06 14:45 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Cc: Krzysztof Kozlowski
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 60 ++-
.../dts/qcom/sm8150-microsoft-surface-duo.dts | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 376 ++++++------------
3 files changed, 157 insertions(+), 281 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
index 87ab0e1ecd16..06d0b6edd48a 100644
--- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
@@ -477,26 +477,26 @@ &pcie1_phy {
&tlmm {
gpio-reserved-ranges = <0 4>;
- sdc2_on: sdc2_on {
- clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <16>; /* 16 MA */
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
- sd-cd {
+ sd-cd-pins {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
@@ -504,26 +504,26 @@ sd-cd {
};
};
- sdc2_off: sdc2_off {
- clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable; /* No pull */
drive-strength = <2>; /* 2 MA */
};
- cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
- data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
- sd-cd {
+ sd-cd-pins {
pins = "gpio96";
function = "gpio";
bias-pull-up; /* pull up */
@@ -531,66 +531,62 @@ sd-cd {
};
};
- usb2phy_ac_en1_default: usb2phy_ac_en1_default {
- mux {
- pins = "gpio113";
- function = "usb2phy_ac";
- bias-disable;
- drive-strength = <2>;
- };
+ usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
+ pins = "gpio113";
+ function = "usb2phy_ac";
+ bias-disable;
+ drive-strength = <2>;
};
- usb2phy_ac_en2_default: usb2phy_ac_en2_default {
- mux {
- pins = "gpio123";
- function = "usb2phy_ac";
- bias-disable;
- drive-strength = <2>;
- };
+ usb2phy_ac_en2_default: usb2phy-ac-en2-default-state {
+ pins = "gpio123";
+ function = "usb2phy_ac";
+ bias-disable;
+ drive-strength = <2>;
};
- ethernet_defaults: ethernet-defaults {
- mdc {
+ ethernet_defaults: ethernet-defaults-state {
+ mdc-pins {
pins = "gpio7";
function = "rgmii";
bias-pull-up;
};
- mdio {
+ mdio-pins {
pins = "gpio59";
function = "rgmii";
bias-pull-up;
};
- rgmii-rx {
+ rgmii-rx-pins {
pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
function = "rgmii";
bias-disable;
drive-strength = <2>;
};
- rgmii-tx {
+ rgmii-tx-pins {
pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
function = "rgmii";
bias-pull-up;
drive-strength = <16>;
};
- phy-intr {
+ phy-intr-pins {
pins = "gpio124";
function = "emac_phy";
bias-disable;
drive-strength = <8>;
};
- pps {
+ pps-pins {
pins = "gpio81";
function = "emac_pps";
bias-disable;
drive-strength = <8>;
};
- phy-reset {
+ phy-reset-pins {
pins = "gpio79";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
index bb278ecac3fa..5397fba9417b 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
@@ -475,7 +475,7 @@ &pon_resin {
&tlmm {
gpio-reserved-ranges = <126 4>;
- da7280_intr_default: da7280-intr-default {
+ da7280_intr_default: da7280-intr-default-state {
pins = "gpio42";
function = "gpio";
bias-pull-up;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cef8c4f4f0ff..18195ae2d021 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2276,422 +2276,302 @@ tlmm: pinctrl@3100000 {
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
- qup_i2c0_default: qup-i2c0-default {
- mux {
- pins = "gpio0", "gpio1";
- function = "qup0";
- };
-
- config {
- pins = "gpio0", "gpio1";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ drive-strength = <0x02>;
+ bias-disable;
};
- qup_spi0_default: qup-spi0-default {
+ qup_spi0_default: qup-spi0-default-state {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
drive-strength = <6>;
bias-disable;
};
- qup_i2c1_default: qup-i2c1-default {
- mux {
- pins = "gpio114", "gpio115";
- function = "qup1";
- };
-
- config {
- pins = "gpio114", "gpio115";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio114", "gpio115";
+ function = "qup1";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi1_default: qup-spi1-default {
+ qup_spi1_default: qup-spi1-default-state {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "qup1";
drive-strength = <6>;
bias-disable;
};
- qup_i2c2_default: qup-i2c2-default {
- mux {
- pins = "gpio126", "gpio127";
- function = "qup2";
- };
-
- config {
- pins = "gpio126", "gpio127";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio126", "gpio127";
+ function = "qup2";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi2_default: qup-spi2-default {
+ qup_spi2_default: qup-spi2-default-state {
pins = "gpio126", "gpio127", "gpio128", "gpio129";
function = "qup2";
drive-strength = <6>;
bias-disable;
};
- qup_i2c3_default: qup-i2c3-default {
- mux {
- pins = "gpio144", "gpio145";
- function = "qup3";
- };
-
- config {
- pins = "gpio144", "gpio145";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio144", "gpio145";
+ function = "qup3";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi3_default: qup-spi3-default {
+ qup_spi3_default: qup-spi3-default-state {
pins = "gpio144", "gpio145", "gpio146", "gpio147";
function = "qup3";
drive-strength = <6>;
bias-disable;
};
- qup_i2c4_default: qup-i2c4-default {
- mux {
- pins = "gpio51", "gpio52";
- function = "qup4";
- };
-
- config {
- pins = "gpio51", "gpio52";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio51", "gpio52";
+ function = "qup4";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi4_default: qup-spi4-default {
+ qup_spi4_default: qup-spi4-default-state {
pins = "gpio51", "gpio52", "gpio53", "gpio54";
function = "qup4";
drive-strength = <6>;
bias-disable;
};
- qup_i2c5_default: qup-i2c5-default {
- mux {
- pins = "gpio121", "gpio122";
- function = "qup5";
- };
-
- config {
- pins = "gpio121", "gpio122";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio121", "gpio122";
+ function = "qup5";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi5_default: qup-spi5-default {
+ qup_spi5_default: qup-spi5-default-state {
pins = "gpio119", "gpio120", "gpio121", "gpio122";
function = "qup5";
drive-strength = <6>;
bias-disable;
};
- qup_i2c6_default: qup-i2c6-default {
- mux {
- pins = "gpio6", "gpio7";
- function = "qup6";
- };
-
- config {
- pins = "gpio6", "gpio7";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup6";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi6_default: qup-spi6_default {
+ qup_spi6_default: qup-spi6_default-state {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
bias-disable;
};
- qup_i2c7_default: qup-i2c7-default {
- mux {
- pins = "gpio98", "gpio99";
- function = "qup7";
- };
-
- config {
- pins = "gpio98", "gpio99";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio98", "gpio99";
+ function = "qup7";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi7_default: qup-spi7_default {
+ qup_spi7_default: qup-spi7_default-state {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
bias-disable;
};
- qup_i2c8_default: qup-i2c8-default {
- mux {
- pins = "gpio88", "gpio89";
- function = "qup8";
- };
-
- config {
- pins = "gpio88", "gpio89";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio88", "gpio89";
+ function = "qup8";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi8_default: qup-spi8-default {
+ qup_spi8_default: qup-spi8-default-state {
pins = "gpio88", "gpio89", "gpio90", "gpio91";
function = "qup8";
drive-strength = <6>;
bias-disable;
};
- qup_i2c9_default: qup-i2c9-default {
- mux {
- pins = "gpio39", "gpio40";
- function = "qup9";
- };
-
- config {
- pins = "gpio39", "gpio40";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio39", "gpio40";
+ function = "qup9";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi9_default: qup-spi9-default {
+ qup_spi9_default: qup-spi9-default-state {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "qup9";
drive-strength = <6>;
bias-disable;
};
- qup_i2c10_default: qup-i2c10-default {
- mux {
- pins = "gpio9", "gpio10";
- function = "qup10";
- };
-
- config {
- pins = "gpio9", "gpio10";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio9", "gpio10";
+ function = "qup10";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi10_default: qup-spi10-default {
+ qup_spi10_default: qup-spi10-default-state {
pins = "gpio9", "gpio10", "gpio11", "gpio12";
function = "qup10";
drive-strength = <6>;
bias-disable;
};
- qup_i2c11_default: qup-i2c11-default {
- mux {
- pins = "gpio94", "gpio95";
- function = "qup11";
- };
-
- config {
- pins = "gpio94", "gpio95";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio94", "gpio95";
+ function = "qup11";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi11_default: qup-spi11-default {
+ qup_spi11_default: qup-spi11-default-state {
pins = "gpio92", "gpio93", "gpio94", "gpio95";
function = "qup11";
drive-strength = <6>;
bias-disable;
};
- qup_i2c12_default: qup-i2c12-default {
- mux {
- pins = "gpio83", "gpio84";
- function = "qup12";
- };
-
- config {
- pins = "gpio83", "gpio84";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c12_default: qup-i2c12-default-state {
+ pins = "gpio83", "gpio84";
+ function = "qup12";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi12_default: qup-spi12-default {
+ qup_spi12_default: qup-spi12-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup12";
drive-strength = <6>;
bias-disable;
};
- qup_i2c13_default: qup-i2c13-default {
- mux {
- pins = "gpio43", "gpio44";
- function = "qup13";
- };
-
- config {
- pins = "gpio43", "gpio44";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c13_default: qup-i2c13-default-state {
+ pins = "gpio43", "gpio44";
+ function = "qup13";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi13_default: qup-spi13-default {
+ qup_spi13_default: qup-spi13-default-state {
pins = "gpio43", "gpio44", "gpio45", "gpio46";
function = "qup13";
drive-strength = <6>;
bias-disable;
};
- qup_i2c14_default: qup-i2c14-default {
- mux {
- pins = "gpio47", "gpio48";
- function = "qup14";
- };
-
- config {
- pins = "gpio47", "gpio48";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c14_default: qup-i2c14-default-state {
+ pins = "gpio47", "gpio48";
+ function = "qup14";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi14_default: qup-spi14-default {
+ qup_spi14_default: qup-spi14-default-state {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
function = "qup14";
drive-strength = <6>;
bias-disable;
};
- qup_i2c15_default: qup-i2c15-default {
- mux {
- pins = "gpio27", "gpio28";
- function = "qup15";
- };
-
- config {
- pins = "gpio27", "gpio28";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c15_default: qup-i2c15-default-state {
+ pins = "gpio27", "gpio28";
+ function = "qup15";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi15_default: qup-spi15-default {
+ qup_spi15_default: qup-spi15-default-state {
pins = "gpio27", "gpio28", "gpio29", "gpio30";
function = "qup15";
drive-strength = <6>;
bias-disable;
};
- qup_i2c16_default: qup-i2c16-default {
- mux {
- pins = "gpio86", "gpio85";
- function = "qup16";
- };
-
- config {
- pins = "gpio86", "gpio85";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c16_default: qup-i2c16-default-state {
+ pins = "gpio86", "gpio85";
+ function = "qup16";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi16_default: qup-spi16-default {
+ qup_spi16_default: qup-spi16-default-state {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup16";
drive-strength = <6>;
bias-disable;
};
- qup_i2c17_default: qup-i2c17-default {
- mux {
- pins = "gpio55", "gpio56";
- function = "qup17";
- };
-
- config {
- pins = "gpio55", "gpio56";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c17_default: qup-i2c17-default-state {
+ pins = "gpio55", "gpio56";
+ function = "qup17";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi17_default: qup-spi17-default {
+ qup_spi17_default: qup-spi17-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup17";
drive-strength = <6>;
bias-disable;
};
- qup_i2c18_default: qup-i2c18-default {
- mux {
- pins = "gpio23", "gpio24";
- function = "qup18";
- };
-
- config {
- pins = "gpio23", "gpio24";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c18_default: qup-i2c18-default-state {
+ pins = "gpio23", "gpio24";
+ function = "qup18";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi18_default: qup-spi18-default {
+ qup_spi18_default: qup-spi18-default-state {
pins = "gpio23", "gpio24", "gpio25", "gpio26";
function = "qup18";
drive-strength = <6>;
bias-disable;
};
- qup_i2c19_default: qup-i2c19-default {
- mux {
- pins = "gpio57", "gpio58";
- function = "qup19";
- };
-
- config {
- pins = "gpio57", "gpio58";
- drive-strength = <0x02>;
- bias-disable;
- };
+ qup_i2c19_default: qup-i2c19-default-state {
+ pins = "gpio57", "gpio58";
+ function = "qup19";
+ drive-strength = <2>;
+ bias-disable;
};
- qup_spi19_default: qup-spi19-default {
+ qup_spi19_default: qup-spi19-default-state {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup19";
drive-strength = <6>;
bias-disable;
};
- pcie0_default_state: pcie0-default {
- perst {
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
pins = "gpio35";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio36";
function = "pci_e0";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio37";
function = "gpio";
drive-strength = <2>;
@@ -2699,22 +2579,22 @@ wake {
};
};
- pcie1_default_state: pcie1-default {
- perst {
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
pins = "gpio102";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
- clkreq {
+ clkreq-pins {
pins = "gpio103";
function = "pci_e1";
drive-strength = <2>;
bias-pull-up;
};
- wake {
+ wake-pins {
pins = "gpio104";
function = "gpio";
drive-strength = <2>;
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema
2022-10-06 14:45 [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Krzysztof Kozlowski
@ 2022-10-06 14:45 ` Krzysztof Kozlowski
2022-10-06 20:55 ` Rob Herring
2022-10-07 3:04 ` Bjorn Andersson
2022-10-07 2:57 ` [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Bjorn Andersson
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-06 14:45 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Convert Qualcomm SM8150 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/pinctrl/qcom,sm8150-pinctrl.txt | 190 ------------------
.../bindings/pinctrl/qcom,sm8150-pinctrl.yaml | 178 ++++++++++++++++
2 files changed, 178 insertions(+), 190 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
deleted file mode 100644
index fa37733e5102..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
+++ /dev/null
@@ -1,190 +0,0 @@
-Qualcomm SM8150 TLMM block
-
-This binding describes the Top Level Mode Multiplexer block found in the
-QCS404 platform.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be "qcom,sm8150-pinctrl"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the base address and size of the north, south, west
- and east TLMM tiles.
-
-- reg-names:
- Usage: required
- Value type: <prop-encoded-array>
- Defintiion: names for the cells of reg, must contain "north", "south"
- "west" and "east".
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: should specify the TLMM summary IRQ.
-
-- interrupt-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as an interrupt controller
-
-- #interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/interrupt-controller/irq.h>
-
-- gpio-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as a gpio controller
-
-- #gpio-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/gpio/gpio.h>
-
-- gpio-ranges:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: see ../gpio/gpio.txt
-
-- gpio-reserved-ranges:
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: see ../gpio/gpio.txt
-
-Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
-a general description of GPIO and interrupt bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-The pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-
-PIN CONFIGURATION NODES:
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pin configuration subnode:
-
-- pins:
- Usage: required
- Value type: <string-array>
- Definition: List of gpio pins affected by the properties specified in
- this subnode.
-
- Valid pins are:
- gpio0-gpio149
- Supports mux, bias and drive-strength
-
- sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
- sdc2_data sdc1_rclk
- Supports bias and drive-strength
-
- ufs_reset
- Supports bias and drive-strength
-
-- function:
- Usage: required
- Value type: <string>
- Definition: Specify the alternative function to be configured for the
- specified pins. Functions are only valid for gpio pins.
- Valid values are:
-
- adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
- atest_char0, atest_char1, atest_char2, atest_char3,
- audio_ref, atest_usb1, atest_usb2, atest_usb10,
- atest_usb11, atest_usb12, atest_usb13, atest_usb20,
- atest_usb21, atest_usb22, atest_usb2, atest_usb23,
- btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
- cci_timer1, cci_timer2, cci_timer3, cci_timer4,
- cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
- ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
- emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
- hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
- lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
- mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
- pa_indicator, pci_e0, phase_flag, pll_bypassnl,
- pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
- prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
- qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
- qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
- qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
- qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
- sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
- tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
- tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
- usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
- wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
-
-- bias-disable:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configued as no pull.
-
-- bias-pull-down:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configued as pull down.
-
-- bias-pull-up:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configued as pull up.
-
-- output-high:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- high.
- Not valid for sdc pins.
-
-- output-low:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- low.
- Not valid for sdc pins.
-
-- drive-strength:
- Usage: optional
- Value type: <u32>
- Definition: Selects the drive strength for the specified pins, in mA.
- Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
-
-Example:
-
- tlmm: pinctrl@3000000 {
- compatible = "qcom,sm8150-pinctrl";
- reg = <0x03100000 0x300000>,
- <0x03500000 0x300000>,
- <0x03900000 0x300000>,
- <0x03D00000 0x300000>;
- reg-names = "west", "east", "north", "south";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 175>;
- gpio-reserved-ranges = <0 4>, <126 4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
new file mode 100644
index 000000000000..41066d88dc57
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8150 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm8150-pinctrl
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: west
+ - const: east
+ - const: north
+ - const: south
+
+ interrupts: true
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 88
+
+ gpio-line-names:
+ maxItems: 175
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8150-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8150-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8150-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
+ - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
+ atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
+ atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
+ atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
+ atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
+ cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
+ ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
+ gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
+ jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
+ mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
+ pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
+ pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
+ qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
+ qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
+ qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
+ qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
+ qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
+ ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
+ tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
+ usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
+ wlan2_adc0, wlan2_adc1, wmss_reset ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@3100000 {
+ compatible = "qcom,sm8150-pinctrl";
+ reg = <0x03100000 0x300000>,
+ <0x03500000 0x300000>,
+ <0x03900000 0x300000>,
+ <0x03d00000 0x300000>;
+ reg-names = "west", "east", "north", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-ranges = <&tlmm 0 0 176>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+
+ qup-spi0-default-state {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "qup0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pcie1-default-state {
+ perst-pins {
+ pins = "gpio102";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio103";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
@ 2022-10-06 20:55 ` Rob Herring
2022-10-07 3:04 ` Bjorn Andersson
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring @ 2022-10-06 20:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-gpio, linux-arm-msm, linux-kernel, Krzysztof Kozlowski,
Linus Walleij, Andy Gross, Konrad Dybcio, Bjorn Andersson,
devicetree, Rob Herring
On Thu, 06 Oct 2022 16:45:18 +0200, Krzysztof Kozlowski wrote:
> Convert Qualcomm SM8150 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/pinctrl/qcom,sm8150-pinctrl.txt | 190 ------------------
> .../bindings/pinctrl/qcom,sm8150-pinctrl.yaml | 178 ++++++++++++++++
> 2 files changed, 178 insertions(+), 190 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
2022-10-06 14:45 [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Krzysztof Kozlowski
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
@ 2022-10-07 2:57 ` Bjorn Andersson
2022-10-07 6:59 ` Krzysztof Kozlowski
2022-10-07 19:43 ` Konrad Dybcio
2022-10-18 3:05 ` (subset) " Bjorn Andersson
3 siblings, 1 reply; 8+ messages in thread
From: Bjorn Andersson @ 2022-10-07 2:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Konrad Dybcio, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-gpio, devicetree,
linux-kernel
On Thu, Oct 06, 2022 at 04:45:17PM +0200, Krzysztof Kozlowski wrote:
> DT schema expects TLMM pin configuration nodes to be named with
> '-state' suffix and their optional children with '-pins' suffix.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
> ---
> arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 60 ++-
> .../dts/qcom/sm8150-microsoft-surface-duo.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 376 ++++++------------
> 3 files changed, 157 insertions(+), 281 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> index 87ab0e1ecd16..06d0b6edd48a 100644
> --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> @@ -477,26 +477,26 @@ &pcie1_phy {
> &tlmm {
> gpio-reserved-ranges = <0 4>;
>
> - sdc2_on: sdc2_on {
> - clk {
> + sdc2_on: sdc2-on-state {
> + clk-pins {
> pins = "sdc2_clk";
> bias-disable; /* No pull */
> drive-strength = <16>; /* 16 MA */
> };
>
> - cmd {
> + cmd-pins {
> pins = "sdc2_cmd";
> bias-pull-up; /* pull up */
> drive-strength = <16>; /* 16 MA */
> };
>
> - data {
> + data-pins {
> pins = "sdc2_data";
> bias-pull-up; /* pull up */
> drive-strength = <16>; /* 16 MA */
> };
>
> - sd-cd {
> + sd-cd-pins {
> pins = "gpio96";
> function = "gpio";
> bias-pull-up; /* pull up */
> @@ -504,26 +504,26 @@ sd-cd {
> };
> };
>
> - sdc2_off: sdc2_off {
> - clk {
> + sdc2_off: sdc2-off-state {
> + clk-pins {
> pins = "sdc2_clk";
> bias-disable; /* No pull */
> drive-strength = <2>; /* 2 MA */
> };
>
> - cmd {
> + cmd-pins {
> pins = "sdc2_cmd";
> bias-pull-up; /* pull up */
> drive-strength = <2>; /* 2 MA */
> };
>
> - data {
> + data-pins {
> pins = "sdc2_data";
> bias-pull-up; /* pull up */
> drive-strength = <2>; /* 2 MA */
> };
>
> - sd-cd {
> + sd-cd-pins {
> pins = "gpio96";
> function = "gpio";
> bias-pull-up; /* pull up */
> @@ -531,66 +531,62 @@ sd-cd {
> };
> };
>
> - usb2phy_ac_en1_default: usb2phy_ac_en1_default {
> - mux {
> - pins = "gpio113";
> - function = "usb2phy_ac";
> - bias-disable;
> - drive-strength = <2>;
> - };
> + usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
> + pins = "gpio113";
> + function = "usb2phy_ac";
> + bias-disable;
> + drive-strength = <2>;
> };
>
> - usb2phy_ac_en2_default: usb2phy_ac_en2_default {
> - mux {
> - pins = "gpio123";
> - function = "usb2phy_ac";
> - bias-disable;
> - drive-strength = <2>;
> - };
> + usb2phy_ac_en2_default: usb2phy-ac-en2-default-state {
> + pins = "gpio123";
> + function = "usb2phy_ac";
> + bias-disable;
> + drive-strength = <2>;
> };
>
> - ethernet_defaults: ethernet-defaults {
> - mdc {
> + ethernet_defaults: ethernet-defaults-state {
> + mdc-pins {
> pins = "gpio7";
> function = "rgmii";
> bias-pull-up;
> };
>
> - mdio {
> + mdio-pins {
> pins = "gpio59";
> function = "rgmii";
> bias-pull-up;
> };
>
> - rgmii-rx {
> + rgmii-rx-pins {
> pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
> function = "rgmii";
> bias-disable;
> drive-strength = <2>;
> };
>
> - rgmii-tx {
> + rgmii-tx-pins {
> pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
> function = "rgmii";
> bias-pull-up;
> drive-strength = <16>;
> };
>
> - phy-intr {
> + phy-intr-pins {
> pins = "gpio124";
> function = "emac_phy";
> bias-disable;
> drive-strength = <8>;
> };
>
> - pps {
> + pps-pins {
> pins = "gpio81";
> function = "emac_pps";
> bias-disable;
> drive-strength = <8>;
> };
>
> - phy-reset {
> + phy-reset-pins {
> pins = "gpio79";
> function = "gpio";
> bias-pull-up;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> index bb278ecac3fa..5397fba9417b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> @@ -475,7 +475,7 @@ &pon_resin {
> &tlmm {
> gpio-reserved-ranges = <126 4>;
>
> - da7280_intr_default: da7280-intr-default {
> + da7280_intr_default: da7280-intr-default-state {
> pins = "gpio42";
> function = "gpio";
> bias-pull-up;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index cef8c4f4f0ff..18195ae2d021 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2276,422 +2276,302 @@ tlmm: pinctrl@3100000 {
> #interrupt-cells = <2>;
> wakeup-parent = <&pdc>;
>
> - qup_i2c0_default: qup-i2c0-default {
> - mux {
> - pins = "gpio0", "gpio1";
> - function = "qup0";
> - };
> -
> - config {
> - pins = "gpio0", "gpio1";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + drive-strength = <0x02>;
> + bias-disable;
> };
>
> - qup_spi0_default: qup-spi0-default {
> + qup_spi0_default: qup-spi0-default-state {
> pins = "gpio0", "gpio1", "gpio2", "gpio3";
> function = "qup0";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c1_default: qup-i2c1-default {
> - mux {
> - pins = "gpio114", "gpio115";
> - function = "qup1";
> - };
> -
> - config {
> - pins = "gpio114", "gpio115";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio114", "gpio115";
> + function = "qup1";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi1_default: qup-spi1-default {
> + qup_spi1_default: qup-spi1-default-state {
> pins = "gpio114", "gpio115", "gpio116", "gpio117";
> function = "qup1";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c2_default: qup-i2c2-default {
> - mux {
> - pins = "gpio126", "gpio127";
> - function = "qup2";
> - };
> -
> - config {
> - pins = "gpio126", "gpio127";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio126", "gpio127";
> + function = "qup2";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi2_default: qup-spi2-default {
> + qup_spi2_default: qup-spi2-default-state {
> pins = "gpio126", "gpio127", "gpio128", "gpio129";
> function = "qup2";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c3_default: qup-i2c3-default {
> - mux {
> - pins = "gpio144", "gpio145";
> - function = "qup3";
> - };
> -
> - config {
> - pins = "gpio144", "gpio145";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio144", "gpio145";
> + function = "qup3";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi3_default: qup-spi3-default {
> + qup_spi3_default: qup-spi3-default-state {
> pins = "gpio144", "gpio145", "gpio146", "gpio147";
> function = "qup3";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c4_default: qup-i2c4-default {
> - mux {
> - pins = "gpio51", "gpio52";
> - function = "qup4";
> - };
> -
> - config {
> - pins = "gpio51", "gpio52";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio51", "gpio52";
> + function = "qup4";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi4_default: qup-spi4-default {
> + qup_spi4_default: qup-spi4-default-state {
> pins = "gpio51", "gpio52", "gpio53", "gpio54";
> function = "qup4";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c5_default: qup-i2c5-default {
> - mux {
> - pins = "gpio121", "gpio122";
> - function = "qup5";
> - };
> -
> - config {
> - pins = "gpio121", "gpio122";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio121", "gpio122";
> + function = "qup5";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi5_default: qup-spi5-default {
> + qup_spi5_default: qup-spi5-default-state {
> pins = "gpio119", "gpio120", "gpio121", "gpio122";
> function = "qup5";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c6_default: qup-i2c6-default {
> - mux {
> - pins = "gpio6", "gpio7";
> - function = "qup6";
> - };
> -
> - config {
> - pins = "gpio6", "gpio7";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup6";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi6_default: qup-spi6_default {
> + qup_spi6_default: qup-spi6_default-state {
> pins = "gpio4", "gpio5", "gpio6", "gpio7";
> function = "qup6";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c7_default: qup-i2c7-default {
> - mux {
> - pins = "gpio98", "gpio99";
> - function = "qup7";
> - };
> -
> - config {
> - pins = "gpio98", "gpio99";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio98", "gpio99";
> + function = "qup7";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi7_default: qup-spi7_default {
> + qup_spi7_default: qup-spi7_default-state {
> pins = "gpio98", "gpio99", "gpio100", "gpio101";
> function = "qup7";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c8_default: qup-i2c8-default {
> - mux {
> - pins = "gpio88", "gpio89";
> - function = "qup8";
> - };
> -
> - config {
> - pins = "gpio88", "gpio89";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio88", "gpio89";
> + function = "qup8";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi8_default: qup-spi8-default {
> + qup_spi8_default: qup-spi8-default-state {
> pins = "gpio88", "gpio89", "gpio90", "gpio91";
> function = "qup8";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c9_default: qup-i2c9-default {
> - mux {
> - pins = "gpio39", "gpio40";
> - function = "qup9";
> - };
> -
> - config {
> - pins = "gpio39", "gpio40";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio39", "gpio40";
> + function = "qup9";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi9_default: qup-spi9-default {
> + qup_spi9_default: qup-spi9-default-state {
> pins = "gpio39", "gpio40", "gpio41", "gpio42";
> function = "qup9";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c10_default: qup-i2c10-default {
> - mux {
> - pins = "gpio9", "gpio10";
> - function = "qup10";
> - };
> -
> - config {
> - pins = "gpio9", "gpio10";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio9", "gpio10";
> + function = "qup10";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi10_default: qup-spi10-default {
> + qup_spi10_default: qup-spi10-default-state {
> pins = "gpio9", "gpio10", "gpio11", "gpio12";
> function = "qup10";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c11_default: qup-i2c11-default {
> - mux {
> - pins = "gpio94", "gpio95";
> - function = "qup11";
> - };
> -
> - config {
> - pins = "gpio94", "gpio95";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio94", "gpio95";
> + function = "qup11";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi11_default: qup-spi11-default {
> + qup_spi11_default: qup-spi11-default-state {
> pins = "gpio92", "gpio93", "gpio94", "gpio95";
> function = "qup11";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c12_default: qup-i2c12-default {
> - mux {
> - pins = "gpio83", "gpio84";
> - function = "qup12";
> - };
> -
> - config {
> - pins = "gpio83", "gpio84";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio83", "gpio84";
> + function = "qup12";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi12_default: qup-spi12-default {
> + qup_spi12_default: qup-spi12-default-state {
> pins = "gpio83", "gpio84", "gpio85", "gpio86";
> function = "qup12";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c13_default: qup-i2c13-default {
> - mux {
> - pins = "gpio43", "gpio44";
> - function = "qup13";
> - };
> -
> - config {
> - pins = "gpio43", "gpio44";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio43", "gpio44";
> + function = "qup13";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi13_default: qup-spi13-default {
> + qup_spi13_default: qup-spi13-default-state {
> pins = "gpio43", "gpio44", "gpio45", "gpio46";
> function = "qup13";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c14_default: qup-i2c14-default {
> - mux {
> - pins = "gpio47", "gpio48";
> - function = "qup14";
> - };
> -
> - config {
> - pins = "gpio47", "gpio48";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio47", "gpio48";
> + function = "qup14";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi14_default: qup-spi14-default {
> + qup_spi14_default: qup-spi14-default-state {
> pins = "gpio47", "gpio48", "gpio49", "gpio50";
> function = "qup14";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c15_default: qup-i2c15-default {
> - mux {
> - pins = "gpio27", "gpio28";
> - function = "qup15";
> - };
> -
> - config {
> - pins = "gpio27", "gpio28";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio27", "gpio28";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi15_default: qup-spi15-default {
> + qup_spi15_default: qup-spi15-default-state {
> pins = "gpio27", "gpio28", "gpio29", "gpio30";
> function = "qup15";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c16_default: qup-i2c16-default {
> - mux {
> - pins = "gpio86", "gpio85";
> - function = "qup16";
> - };
> -
> - config {
> - pins = "gpio86", "gpio85";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c16_default: qup-i2c16-default-state {
> + pins = "gpio86", "gpio85";
> + function = "qup16";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi16_default: qup-spi16-default {
> + qup_spi16_default: qup-spi16-default-state {
> pins = "gpio83", "gpio84", "gpio85", "gpio86";
> function = "qup16";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c17_default: qup-i2c17-default {
> - mux {
> - pins = "gpio55", "gpio56";
> - function = "qup17";
> - };
> -
> - config {
> - pins = "gpio55", "gpio56";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c17_default: qup-i2c17-default-state {
> + pins = "gpio55", "gpio56";
> + function = "qup17";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi17_default: qup-spi17-default {
> + qup_spi17_default: qup-spi17-default-state {
> pins = "gpio55", "gpio56", "gpio57", "gpio58";
> function = "qup17";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c18_default: qup-i2c18-default {
> - mux {
> - pins = "gpio23", "gpio24";
> - function = "qup18";
> - };
> -
> - config {
> - pins = "gpio23", "gpio24";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c18_default: qup-i2c18-default-state {
> + pins = "gpio23", "gpio24";
> + function = "qup18";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi18_default: qup-spi18-default {
> + qup_spi18_default: qup-spi18-default-state {
> pins = "gpio23", "gpio24", "gpio25", "gpio26";
> function = "qup18";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c19_default: qup-i2c19-default {
> - mux {
> - pins = "gpio57", "gpio58";
> - function = "qup19";
> - };
> -
> - config {
> - pins = "gpio57", "gpio58";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c19_default: qup-i2c19-default-state {
> + pins = "gpio57", "gpio58";
> + function = "qup19";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi19_default: qup-spi19-default {
> + qup_spi19_default: qup-spi19-default-state {
> pins = "gpio55", "gpio56", "gpio57", "gpio58";
> function = "qup19";
> drive-strength = <6>;
> bias-disable;
> };
>
> - pcie0_default_state: pcie0-default {
> - perst {
> + pcie0_default_state: pcie0-default-state {
> + perst-pins {
> pins = "gpio35";
> function = "gpio";
> drive-strength = <2>;
> bias-pull-down;
> };
>
> - clkreq {
> + clkreq-pins {
> pins = "gpio36";
> function = "pci_e0";
> drive-strength = <2>;
> bias-pull-up;
> };
>
> - wake {
> + wake-pins {
> pins = "gpio37";
> function = "gpio";
> drive-strength = <2>;
> @@ -2699,22 +2579,22 @@ wake {
> };
> };
>
> - pcie1_default_state: pcie1-default {
> - perst {
> + pcie1_default_state: pcie1-default-state {
> + perst-pins {
> pins = "gpio102";
> function = "gpio";
> drive-strength = <2>;
> bias-pull-down;
> };
>
> - clkreq {
> + clkreq-pins {
> pins = "gpio103";
> function = "pci_e1";
> drive-strength = <2>;
> bias-pull-up;
> };
>
> - wake {
> + wake-pins {
> pins = "gpio104";
> function = "gpio";
> drive-strength = <2>;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
2022-10-06 20:55 ` Rob Herring
@ 2022-10-07 3:04 ` Bjorn Andersson
1 sibling, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2022-10-07 3:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Konrad Dybcio, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-gpio, devicetree,
linux-kernel
On Thu, Oct 06, 2022 at 04:45:18PM +0200, Krzysztof Kozlowski wrote:
> Convert Qualcomm SM8150 pin controller bindings to DT schema. Keep the
> parsing of pin configuration subnodes consistent with other Qualcomm
> schemas (children named with '-state' suffix, their children with
> '-pins').
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
There are a few differences between the old and new binding, nice to see
those mistakes being corrected.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> .../bindings/pinctrl/qcom,sm8150-pinctrl.txt | 190 ------------------
> .../bindings/pinctrl/qcom,sm8150-pinctrl.yaml | 178 ++++++++++++++++
> 2 files changed, 178 insertions(+), 190 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> deleted file mode 100644
> index fa37733e5102..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.txt
> +++ /dev/null
> @@ -1,190 +0,0 @@
> -Qualcomm SM8150 TLMM block
> -
> -This binding describes the Top Level Mode Multiplexer block found in the
> -QCS404 platform.
> -
> -- compatible:
> - Usage: required
> - Value type: <string>
> - Definition: must be "qcom,sm8150-pinctrl"
> -
> -- reg:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: the base address and size of the north, south, west
> - and east TLMM tiles.
> -
> -- reg-names:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Defintiion: names for the cells of reg, must contain "north", "south"
> - "west" and "east".
> -
> -- interrupts:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: should specify the TLMM summary IRQ.
> -
> -- interrupt-controller:
> - Usage: required
> - Value type: <none>
> - Definition: identifies this node as an interrupt controller
> -
> -- #interrupt-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 2. Specifying the pin number and flags, as defined
> - in <dt-bindings/interrupt-controller/irq.h>
> -
> -- gpio-controller:
> - Usage: required
> - Value type: <none>
> - Definition: identifies this node as a gpio controller
> -
> -- #gpio-cells:
> - Usage: required
> - Value type: <u32>
> - Definition: must be 2. Specifying the pin number and flags, as defined
> - in <dt-bindings/gpio/gpio.h>
> -
> -- gpio-ranges:
> - Usage: required
> - Value type: <prop-encoded-array>
> - Definition: see ../gpio/gpio.txt
> -
> -- gpio-reserved-ranges:
> - Usage: optional
> - Value type: <prop-encoded-array>
> - Definition: see ../gpio/gpio.txt
> -
> -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
> -a general description of GPIO and interrupt bindings.
> -
> -Please refer to pinctrl-bindings.txt in this directory for details of the
> -common pinctrl bindings used by client devices, including the meaning of the
> -phrase "pin configuration node".
> -
> -The pin configuration nodes act as a container for an arbitrary number of
> -subnodes. Each of these subnodes represents some desired configuration for a
> -pin, a group, or a list of pins or groups. This configuration can include the
> -mux function to select on those pin(s)/group(s), and various pin configuration
> -parameters, such as pull-up, drive strength, etc.
> -
> -
> -PIN CONFIGURATION NODES:
> -
> -The name of each subnode is not important; all subnodes should be enumerated
> -and processed purely based on their content.
> -
> -Each subnode only affects those parameters that are explicitly listed. In
> -other words, a subnode that lists a mux function but no pin configuration
> -parameters implies no information about any pin configuration parameters.
> -Similarly, a pin subnode that describes a pullup parameter implies no
> -information about e.g. the mux function.
> -
> -
> -The following generic properties as defined in pinctrl-bindings.txt are valid
> -to specify in a pin configuration subnode:
> -
> -- pins:
> - Usage: required
> - Value type: <string-array>
> - Definition: List of gpio pins affected by the properties specified in
> - this subnode.
> -
> - Valid pins are:
> - gpio0-gpio149
> - Supports mux, bias and drive-strength
> -
> - sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
> - sdc2_data sdc1_rclk
> - Supports bias and drive-strength
> -
> - ufs_reset
> - Supports bias and drive-strength
> -
> -- function:
> - Usage: required
> - Value type: <string>
> - Definition: Specify the alternative function to be configured for the
> - specified pins. Functions are only valid for gpio pins.
> - Valid values are:
> -
> - adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
> - atest_char0, atest_char1, atest_char2, atest_char3,
> - audio_ref, atest_usb1, atest_usb2, atest_usb10,
> - atest_usb11, atest_usb12, atest_usb13, atest_usb20,
> - atest_usb21, atest_usb22, atest_usb2, atest_usb23,
> - btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
> - cci_timer1, cci_timer2, cci_timer3, cci_timer4,
> - cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist,
> - ddr_pxi0, ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd,
> - emac_phy, emac_pps, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> - hs1_mi2s, hs2_mi2s, hs3_mi2s, jitter_bist,
> - lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
> - mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps,
> - pa_indicator, pci_e0, phase_flag, pll_bypassnl,
> - pll_bist, pci_e1, pll_reset, pri_mi2s, pri_mi2s_ws,
> - prng_rosc, qdss, qdss_cti, qlink_request, qlink_enable,
> - qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qua_mi2s,
> - qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8,
> - qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16,
> - qup17, qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii,
> - sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, ter_mi2s,
> - tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
> - tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt,
> - usb2phy_ac, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
> - wlan1_adc1, wlan2_adc0, wlan2_adc1, wmss_reset
> -
> -- bias-disable:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configued as no pull.
> -
> -- bias-pull-down:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configued as pull down.
> -
> -- bias-pull-up:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins should be configued as pull up.
> -
> -- output-high:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins are configured in output mode, driven
> - high.
> - Not valid for sdc pins.
> -
> -- output-low:
> - Usage: optional
> - Value type: <none>
> - Definition: The specified pins are configured in output mode, driven
> - low.
> - Not valid for sdc pins.
> -
> -- drive-strength:
> - Usage: optional
> - Value type: <u32>
> - Definition: Selects the drive strength for the specified pins, in mA.
> - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
> -
> -Example:
> -
> - tlmm: pinctrl@3000000 {
> - compatible = "qcom,sm8150-pinctrl";
> - reg = <0x03100000 0x300000>,
> - <0x03500000 0x300000>,
> - <0x03900000 0x300000>,
> - <0x03D00000 0x300000>;
> - reg-names = "west", "east", "north", "south";
> - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - gpio-ranges = <&tlmm 0 0 175>;
> - gpio-reserved-ranges = <0 4>, <126 4>;
> - interrupt-controller;
> - #interrupt-cells = <2>;
> - };
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
> new file mode 100644
> index 000000000000..41066d88dc57
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml
> @@ -0,0 +1,178 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8150 TLMM pin controller
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> +
> +description:
> + Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC.
> +
> +properties:
> + compatible:
> + const: qcom,sm8150-pinctrl
> +
> + reg:
> + maxItems: 4
> +
> + reg-names:
> + items:
> + - const: west
> + - const: east
> + - const: north
> + - const: south
> +
> + interrupts: true
> + interrupt-controller: true
> + "#interrupt-cells": true
> + gpio-controller: true
> + "#gpio-cells": true
> + gpio-ranges: true
> + wakeup-parent: true
> +
> + gpio-reserved-ranges:
> + minItems: 1
> + maxItems: 88
> +
> + gpio-line-names:
> + maxItems: 175
> +
> +patternProperties:
> + "-state$":
> + oneOf:
> + - $ref: "#/$defs/qcom-sm8150-tlmm-state"
> + - patternProperties:
> + "-pins$":
> + $ref: "#/$defs/qcom-sm8150-tlmm-state"
> + additionalProperties: false
> +
> +$defs:
> + qcom-sm8150-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
> + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> + minItems: 1
> + maxItems: 36
> +
> + function:
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> +
> + enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char,
> + atest_char0, atest_char1, atest_char2, atest_char3, audio_ref,
> + atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12,
> + atest_usb13, atest_usb20, atest_usb21, atest_usb22, atest_usb2,
> + atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
> + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
> + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
> + ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps,
> + gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s,
> + jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1,
> + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator,
> + pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset,
> + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti,
> + qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3,
> + qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4,
> + qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13,
> + qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5,
> + qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu,
> + ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1,
> + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac,
> + usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1,
> + wlan2_adc0, wlan2_adc1, wmss_reset ]
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> + default: 2
> + description:
> + Selects the drive strength for the specified pins, in mA.
> +
> + bias-pull-down: true
> + bias-pull-up: true
> + bias-disable: true
> + input-enable: true
> + output-high: true
> + output-low: true
> +
> + required:
> + - pins
> +
> + additionalProperties: false
> +
> +allOf:
> + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + tlmm: pinctrl@3100000 {
> + compatible = "qcom,sm8150-pinctrl";
> + reg = <0x03100000 0x300000>,
> + <0x03500000 0x300000>,
> + <0x03900000 0x300000>,
> + <0x03d00000 0x300000>;
> + reg-names = "west", "east", "north", "south";
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-ranges = <&tlmm 0 0 176>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + wakeup-parent = <&pdc>;
> +
> + qup-spi0-default-state {
> + pins = "gpio0", "gpio1", "gpio2", "gpio3";
> + function = "qup0";
> + drive-strength = <6>;
> + bias-disable;
> + };
> +
> + pcie1-default-state {
> + perst-pins {
> + pins = "gpio102";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio103";
> + function = "pci_e1";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio104";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> + };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
2022-10-07 2:57 ` [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Bjorn Andersson
@ 2022-10-07 6:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-07 6:59 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Konrad Dybcio, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, linux-gpio, devicetree,
linux-kernel
On 07/10/2022 04:57, Bjorn Andersson wrote:
> On Thu, Oct 06, 2022 at 04:45:17PM +0200, Krzysztof Kozlowski wrote:
>> DT schema expects TLMM pin configuration nodes to be named with
>> '-state' suffix and their optional children with '-pins' suffix.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
This one is a DTS, so it is supposed to go via your tree. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
2022-10-06 14:45 [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Krzysztof Kozlowski
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
2022-10-07 2:57 ` [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Bjorn Andersson
@ 2022-10-07 19:43 ` Konrad Dybcio
2022-10-18 3:05 ` (subset) " Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Konrad Dybcio @ 2022-10-07 19:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Andy Gross, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
On 6.10.2022 16:45, Krzysztof Kozlowski wrote:
> DT schema expects TLMM pin configuration nodes to be named with
> '-state' suffix and their optional children with '-pins' suffix.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 60 ++-
> .../dts/qcom/sm8150-microsoft-surface-duo.dts | 2 +-
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 376 ++++++------------
> 3 files changed, 157 insertions(+), 281 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> index 87ab0e1ecd16..06d0b6edd48a 100644
> --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts
> @@ -477,26 +477,26 @@ &pcie1_phy {
> &tlmm {
> gpio-reserved-ranges = <0 4>;
>
> - sdc2_on: sdc2_on {
> - clk {
> + sdc2_on: sdc2-on-state {
> + clk-pins {
> pins = "sdc2_clk";
> bias-disable; /* No pull */
> drive-strength = <16>; /* 16 MA */
I think these comments could go as well? The properties are rather self-explanatory.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Konrad
> };
>
> - cmd {
> + cmd-pins {
> pins = "sdc2_cmd";
> bias-pull-up; /* pull up */
> drive-strength = <16>; /* 16 MA */
> };
>
> - data {
> + data-pins {
> pins = "sdc2_data";
> bias-pull-up; /* pull up */
> drive-strength = <16>; /* 16 MA */
> };
>
> - sd-cd {
> + sd-cd-pins {
> pins = "gpio96";
> function = "gpio";
> bias-pull-up; /* pull up */
> @@ -504,26 +504,26 @@ sd-cd {
> };
> };
>
> - sdc2_off: sdc2_off {
> - clk {
> + sdc2_off: sdc2-off-state {
> + clk-pins {
> pins = "sdc2_clk";
> bias-disable; /* No pull */
> drive-strength = <2>; /* 2 MA */
> };
>
> - cmd {
> + cmd-pins {
> pins = "sdc2_cmd";
> bias-pull-up; /* pull up */
> drive-strength = <2>; /* 2 MA */
> };
>
> - data {
> + data-pins {
> pins = "sdc2_data";
> bias-pull-up; /* pull up */
> drive-strength = <2>; /* 2 MA */
> };
>
> - sd-cd {
> + sd-cd-pins {
> pins = "gpio96";
> function = "gpio";
> bias-pull-up; /* pull up */
> @@ -531,66 +531,62 @@ sd-cd {
> };
> };
>
> - usb2phy_ac_en1_default: usb2phy_ac_en1_default {
> - mux {
> - pins = "gpio113";
> - function = "usb2phy_ac";
> - bias-disable;
> - drive-strength = <2>;
> - };
> + usb2phy_ac_en1_default: usb2phy-ac-en1-default-state {
> + pins = "gpio113";
> + function = "usb2phy_ac";
> + bias-disable;
> + drive-strength = <2>;
> };
>
> - usb2phy_ac_en2_default: usb2phy_ac_en2_default {
> - mux {
> - pins = "gpio123";
> - function = "usb2phy_ac";
> - bias-disable;
> - drive-strength = <2>;
> - };
> + usb2phy_ac_en2_default: usb2phy-ac-en2-default-state {
> + pins = "gpio123";
> + function = "usb2phy_ac";
> + bias-disable;
> + drive-strength = <2>;
> };
>
> - ethernet_defaults: ethernet-defaults {
> - mdc {
> + ethernet_defaults: ethernet-defaults-state {
> + mdc-pins {
> pins = "gpio7";
> function = "rgmii";
> bias-pull-up;
> };
>
> - mdio {
> + mdio-pins {
> pins = "gpio59";
> function = "rgmii";
> bias-pull-up;
> };
>
> - rgmii-rx {
> + rgmii-rx-pins {
> pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116";
> function = "rgmii";
> bias-disable;
> drive-strength = <2>;
> };
>
> - rgmii-tx {
> + rgmii-tx-pins {
> pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121";
> function = "rgmii";
> bias-pull-up;
> drive-strength = <16>;
> };
>
> - phy-intr {
> + phy-intr-pins {
> pins = "gpio124";
> function = "emac_phy";
> bias-disable;
> drive-strength = <8>;
> };
>
> - pps {
> + pps-pins {
> pins = "gpio81";
> function = "emac_pps";
> bias-disable;
> drive-strength = <8>;
> };
>
> - phy-reset {
> + phy-reset-pins {
> pins = "gpio79";
> function = "gpio";
> bias-pull-up;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> index bb278ecac3fa..5397fba9417b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
> @@ -475,7 +475,7 @@ &pon_resin {
> &tlmm {
> gpio-reserved-ranges = <126 4>;
>
> - da7280_intr_default: da7280-intr-default {
> + da7280_intr_default: da7280-intr-default-state {
> pins = "gpio42";
> function = "gpio";
> bias-pull-up;
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index cef8c4f4f0ff..18195ae2d021 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -2276,422 +2276,302 @@ tlmm: pinctrl@3100000 {
> #interrupt-cells = <2>;
> wakeup-parent = <&pdc>;
>
> - qup_i2c0_default: qup-i2c0-default {
> - mux {
> - pins = "gpio0", "gpio1";
> - function = "qup0";
> - };
> -
> - config {
> - pins = "gpio0", "gpio1";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c0_default: qup-i2c0-default-state {
> + pins = "gpio0", "gpio1";
> + function = "qup0";
> + drive-strength = <0x02>;
> + bias-disable;
> };
>
> - qup_spi0_default: qup-spi0-default {
> + qup_spi0_default: qup-spi0-default-state {
> pins = "gpio0", "gpio1", "gpio2", "gpio3";
> function = "qup0";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c1_default: qup-i2c1-default {
> - mux {
> - pins = "gpio114", "gpio115";
> - function = "qup1";
> - };
> -
> - config {
> - pins = "gpio114", "gpio115";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c1_default: qup-i2c1-default-state {
> + pins = "gpio114", "gpio115";
> + function = "qup1";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi1_default: qup-spi1-default {
> + qup_spi1_default: qup-spi1-default-state {
> pins = "gpio114", "gpio115", "gpio116", "gpio117";
> function = "qup1";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c2_default: qup-i2c2-default {
> - mux {
> - pins = "gpio126", "gpio127";
> - function = "qup2";
> - };
> -
> - config {
> - pins = "gpio126", "gpio127";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c2_default: qup-i2c2-default-state {
> + pins = "gpio126", "gpio127";
> + function = "qup2";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi2_default: qup-spi2-default {
> + qup_spi2_default: qup-spi2-default-state {
> pins = "gpio126", "gpio127", "gpio128", "gpio129";
> function = "qup2";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c3_default: qup-i2c3-default {
> - mux {
> - pins = "gpio144", "gpio145";
> - function = "qup3";
> - };
> -
> - config {
> - pins = "gpio144", "gpio145";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c3_default: qup-i2c3-default-state {
> + pins = "gpio144", "gpio145";
> + function = "qup3";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi3_default: qup-spi3-default {
> + qup_spi3_default: qup-spi3-default-state {
> pins = "gpio144", "gpio145", "gpio146", "gpio147";
> function = "qup3";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c4_default: qup-i2c4-default {
> - mux {
> - pins = "gpio51", "gpio52";
> - function = "qup4";
> - };
> -
> - config {
> - pins = "gpio51", "gpio52";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c4_default: qup-i2c4-default-state {
> + pins = "gpio51", "gpio52";
> + function = "qup4";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi4_default: qup-spi4-default {
> + qup_spi4_default: qup-spi4-default-state {
> pins = "gpio51", "gpio52", "gpio53", "gpio54";
> function = "qup4";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c5_default: qup-i2c5-default {
> - mux {
> - pins = "gpio121", "gpio122";
> - function = "qup5";
> - };
> -
> - config {
> - pins = "gpio121", "gpio122";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c5_default: qup-i2c5-default-state {
> + pins = "gpio121", "gpio122";
> + function = "qup5";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi5_default: qup-spi5-default {
> + qup_spi5_default: qup-spi5-default-state {
> pins = "gpio119", "gpio120", "gpio121", "gpio122";
> function = "qup5";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c6_default: qup-i2c6-default {
> - mux {
> - pins = "gpio6", "gpio7";
> - function = "qup6";
> - };
> -
> - config {
> - pins = "gpio6", "gpio7";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c6_default: qup-i2c6-default-state {
> + pins = "gpio6", "gpio7";
> + function = "qup6";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi6_default: qup-spi6_default {
> + qup_spi6_default: qup-spi6_default-state {
> pins = "gpio4", "gpio5", "gpio6", "gpio7";
> function = "qup6";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c7_default: qup-i2c7-default {
> - mux {
> - pins = "gpio98", "gpio99";
> - function = "qup7";
> - };
> -
> - config {
> - pins = "gpio98", "gpio99";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c7_default: qup-i2c7-default-state {
> + pins = "gpio98", "gpio99";
> + function = "qup7";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi7_default: qup-spi7_default {
> + qup_spi7_default: qup-spi7_default-state {
> pins = "gpio98", "gpio99", "gpio100", "gpio101";
> function = "qup7";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c8_default: qup-i2c8-default {
> - mux {
> - pins = "gpio88", "gpio89";
> - function = "qup8";
> - };
> -
> - config {
> - pins = "gpio88", "gpio89";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c8_default: qup-i2c8-default-state {
> + pins = "gpio88", "gpio89";
> + function = "qup8";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi8_default: qup-spi8-default {
> + qup_spi8_default: qup-spi8-default-state {
> pins = "gpio88", "gpio89", "gpio90", "gpio91";
> function = "qup8";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c9_default: qup-i2c9-default {
> - mux {
> - pins = "gpio39", "gpio40";
> - function = "qup9";
> - };
> -
> - config {
> - pins = "gpio39", "gpio40";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c9_default: qup-i2c9-default-state {
> + pins = "gpio39", "gpio40";
> + function = "qup9";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi9_default: qup-spi9-default {
> + qup_spi9_default: qup-spi9-default-state {
> pins = "gpio39", "gpio40", "gpio41", "gpio42";
> function = "qup9";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c10_default: qup-i2c10-default {
> - mux {
> - pins = "gpio9", "gpio10";
> - function = "qup10";
> - };
> -
> - config {
> - pins = "gpio9", "gpio10";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c10_default: qup-i2c10-default-state {
> + pins = "gpio9", "gpio10";
> + function = "qup10";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi10_default: qup-spi10-default {
> + qup_spi10_default: qup-spi10-default-state {
> pins = "gpio9", "gpio10", "gpio11", "gpio12";
> function = "qup10";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c11_default: qup-i2c11-default {
> - mux {
> - pins = "gpio94", "gpio95";
> - function = "qup11";
> - };
> -
> - config {
> - pins = "gpio94", "gpio95";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c11_default: qup-i2c11-default-state {
> + pins = "gpio94", "gpio95";
> + function = "qup11";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi11_default: qup-spi11-default {
> + qup_spi11_default: qup-spi11-default-state {
> pins = "gpio92", "gpio93", "gpio94", "gpio95";
> function = "qup11";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c12_default: qup-i2c12-default {
> - mux {
> - pins = "gpio83", "gpio84";
> - function = "qup12";
> - };
> -
> - config {
> - pins = "gpio83", "gpio84";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c12_default: qup-i2c12-default-state {
> + pins = "gpio83", "gpio84";
> + function = "qup12";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi12_default: qup-spi12-default {
> + qup_spi12_default: qup-spi12-default-state {
> pins = "gpio83", "gpio84", "gpio85", "gpio86";
> function = "qup12";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c13_default: qup-i2c13-default {
> - mux {
> - pins = "gpio43", "gpio44";
> - function = "qup13";
> - };
> -
> - config {
> - pins = "gpio43", "gpio44";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c13_default: qup-i2c13-default-state {
> + pins = "gpio43", "gpio44";
> + function = "qup13";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi13_default: qup-spi13-default {
> + qup_spi13_default: qup-spi13-default-state {
> pins = "gpio43", "gpio44", "gpio45", "gpio46";
> function = "qup13";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c14_default: qup-i2c14-default {
> - mux {
> - pins = "gpio47", "gpio48";
> - function = "qup14";
> - };
> -
> - config {
> - pins = "gpio47", "gpio48";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c14_default: qup-i2c14-default-state {
> + pins = "gpio47", "gpio48";
> + function = "qup14";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi14_default: qup-spi14-default {
> + qup_spi14_default: qup-spi14-default-state {
> pins = "gpio47", "gpio48", "gpio49", "gpio50";
> function = "qup14";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c15_default: qup-i2c15-default {
> - mux {
> - pins = "gpio27", "gpio28";
> - function = "qup15";
> - };
> -
> - config {
> - pins = "gpio27", "gpio28";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c15_default: qup-i2c15-default-state {
> + pins = "gpio27", "gpio28";
> + function = "qup15";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi15_default: qup-spi15-default {
> + qup_spi15_default: qup-spi15-default-state {
> pins = "gpio27", "gpio28", "gpio29", "gpio30";
> function = "qup15";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c16_default: qup-i2c16-default {
> - mux {
> - pins = "gpio86", "gpio85";
> - function = "qup16";
> - };
> -
> - config {
> - pins = "gpio86", "gpio85";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c16_default: qup-i2c16-default-state {
> + pins = "gpio86", "gpio85";
> + function = "qup16";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi16_default: qup-spi16-default {
> + qup_spi16_default: qup-spi16-default-state {
> pins = "gpio83", "gpio84", "gpio85", "gpio86";
> function = "qup16";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c17_default: qup-i2c17-default {
> - mux {
> - pins = "gpio55", "gpio56";
> - function = "qup17";
> - };
> -
> - config {
> - pins = "gpio55", "gpio56";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c17_default: qup-i2c17-default-state {
> + pins = "gpio55", "gpio56";
> + function = "qup17";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi17_default: qup-spi17-default {
> + qup_spi17_default: qup-spi17-default-state {
> pins = "gpio55", "gpio56", "gpio57", "gpio58";
> function = "qup17";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c18_default: qup-i2c18-default {
> - mux {
> - pins = "gpio23", "gpio24";
> - function = "qup18";
> - };
> -
> - config {
> - pins = "gpio23", "gpio24";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c18_default: qup-i2c18-default-state {
> + pins = "gpio23", "gpio24";
> + function = "qup18";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi18_default: qup-spi18-default {
> + qup_spi18_default: qup-spi18-default-state {
> pins = "gpio23", "gpio24", "gpio25", "gpio26";
> function = "qup18";
> drive-strength = <6>;
> bias-disable;
> };
>
> - qup_i2c19_default: qup-i2c19-default {
> - mux {
> - pins = "gpio57", "gpio58";
> - function = "qup19";
> - };
> -
> - config {
> - pins = "gpio57", "gpio58";
> - drive-strength = <0x02>;
> - bias-disable;
> - };
> + qup_i2c19_default: qup-i2c19-default-state {
> + pins = "gpio57", "gpio58";
> + function = "qup19";
> + drive-strength = <2>;
> + bias-disable;
> };
>
> - qup_spi19_default: qup-spi19-default {
> + qup_spi19_default: qup-spi19-default-state {
> pins = "gpio55", "gpio56", "gpio57", "gpio58";
> function = "qup19";
> drive-strength = <6>;
> bias-disable;
> };
>
> - pcie0_default_state: pcie0-default {
> - perst {
> + pcie0_default_state: pcie0-default-state {
> + perst-pins {
> pins = "gpio35";
> function = "gpio";
> drive-strength = <2>;
> bias-pull-down;
> };
>
> - clkreq {
> + clkreq-pins {
> pins = "gpio36";
> function = "pci_e0";
> drive-strength = <2>;
> bias-pull-up;
> };
>
> - wake {
> + wake-pins {
> pins = "gpio37";
> function = "gpio";
> drive-strength = <2>;
> @@ -2699,22 +2579,22 @@ wake {
> };
> };
>
> - pcie1_default_state: pcie1-default {
> - perst {
> + pcie1_default_state: pcie1-default-state {
> + perst-pins {
> pins = "gpio102";
> function = "gpio";
> drive-strength = <2>;
> bias-pull-down;
> };
>
> - clkreq {
> + clkreq-pins {
> pins = "gpio103";
> function = "pci_e1";
> drive-strength = <2>;
> bias-pull-up;
> };
>
> - wake {
> + wake-pins {
> pins = "gpio104";
> function = "gpio";
> drive-strength = <2>;
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: (subset) [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
2022-10-06 14:45 [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Krzysztof Kozlowski
` (2 preceding siblings ...)
2022-10-07 19:43 ` Konrad Dybcio
@ 2022-10-18 3:05 ` Bjorn Andersson
3 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2022-10-18 3:05 UTC (permalink / raw)
To: linux-gpio, devicetree, linux-kernel, agross,
krzysztof.kozlowski, linus.walleij, robh+dt, linux-arm-msm,
Krzysztof Kozlowski, Konrad Dybcio
On Thu, 6 Oct 2022 16:45:17 +0200, Krzysztof Kozlowski wrote:
> DT schema expects TLMM pin configuration nodes to be named with
> '-state' suffix and their optional children with '-pins' suffix.
>
>
Applied, thanks!
[1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema
commit: 028fe09cda0a0d568e6a7d65b0336d32600b480c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-10-18 3:09 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-06 14:45 [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Krzysztof Kozlowski
2022-10-06 14:45 ` [PATCH 2/2] dt-bindings: pinctrl: qcom,sm8150: convert to dtschema Krzysztof Kozlowski
2022-10-06 20:55 ` Rob Herring
2022-10-07 3:04 ` Bjorn Andersson
2022-10-07 2:57 ` [PATCH 1/2] arm64: dts: qcom: sm8150: align TLMM pin configuration with DT schema Bjorn Andersson
2022-10-07 6:59 ` Krzysztof Kozlowski
2022-10-07 19:43 ` Konrad Dybcio
2022-10-18 3:05 ` (subset) " Bjorn Andersson
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