[PATCH V3 0/5] Add APSS clock driver support for IPQ5332

[Kathiravan T <quic_kathirav@quicinc.com>]

This series adds support for the APSS clock to bump the CPU frequency
above 800MHz.

APSS PLL found in the IPQ5332 is of type Stromer Plus. However the
existing IPQ targets uses the Huayra PLL. So the driver has to
refactored to accommodate the different PLL types. The first patch in
the series does the refactoring, which can be independenty merged.

For the Stromer PLL separate function clk_stromer_pll_configure is
introduced, so the 3rd patch in the series depends on the below patch
https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/

DTS patch depends on the IPQ5332 baseport series
https://lore.kernel.org/linux-arm-msm/20230130114702.20606-1-quic_kathirav@quicinc.com/

Changes since V2:
	- Pick up R-b tags and sort the node in DTS
	- V2 can be found at
	   https://lore.kernel.org/linux-arm-msm/20230208042850.1687-1-quic_kathirav@quicinc.com/

Changes since V1:
	- Dropped the patch 5/6, since the fallback mechanism for compatible
	  is introduced to avoid bloating the of_device_id table
	- V1 can be found at
	  https://lore.kernel.org/linux-arm-msm/20230202145208.2328032-1-quic_kathirav@quicinc.com/


Kathiravan T (5):
  clk: qcom: apss-ipq-pll: refactor the driver to accommodate different
    PLL types
  dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible
  clk: qcom: apss-ipq-pll: add support for IPQ5332
  dt-bindings: mailbox: qcom: add compatible for the IPQ5332 SoC
  arm64: dts: qcom: ipq5332: enable the CPUFreq support

 .../bindings/clock/qcom,a53pll.yaml           |   1 +
 .../mailbox/qcom,apcs-kpss-global.yaml        |  18 ++-
 arch/arm64/boot/dts/qcom/ipq5332.dtsi         |  37 ++++++
 drivers/clk/qcom/apss-ipq-pll.c               | 116 +++++++++++++++---
 4 files changed, 147 insertions(+), 25 deletions(-)

-- 
2.17.1