Re: [PATCH v2 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes

[Varadarajan Narayanan <quic_varada@quicinc.com>]

On Tue, Mar 21, 2023 at 02:23:26PM +0300, Dmitry Baryshkov wrote:
>
>
> On 21 March 2023 11:54:25 GMT+03:00, Varadarajan Narayanan <quic_varada@quicinc.com> wrote:
> >Add USB phy and controller related nodes
> >
> >Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> >
> >---
> > Changes in v2:
> >	- Fixed issues flagged by Krzysztof
> >	- Fix issues reported by make dtbs_check
> >	- Remove NOC related clocks (to be added with proper
> >	  interconnect support)
> >---
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 86 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >index 2bb4053..513da74 100644
> >--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >@@ -829,6 +829,92 @@
> > 			msi-parent = <&v2m0>;
> > 			status = "disabled";
> > 		};
>
> The last device node is pci@28000000. Thus you are trying to
> add all usb nodes at the wrong place. Please move them so that
> all nodes are still sorted by the address part.

Ok. Will reorder them.

Thanks
Varada

>
>
> >+
> >+		qusb_phy_0: phy@7b000 {
> >+			compatible = "qcom,ipq9574-qusb2-phy";
> >+			reg = <0x07b000 0x180>;
> >+			#phy-cells = <0>;
> >+
> >+			clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> >+				<&xo_board_clk>;
> >+			clock-names = "cfg_ahb", "ref";
> >+
> >+			resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> >+			status = "disabled";
> >+		};
> >+
> >+		ssphy_0: phy@7d000 {
> >+			compatible = "qcom,ipq9574-qmp-usb3-phy";
> >+			reg = <0x7d000 0x1c4>;
> >+			#clock-cells = <1>;
> >+			#address-cells = <1>;
> >+			#size-cells = <1>;
> >+			ranges;
> >+
> >+			clocks = <&gcc GCC_USB0_AUX_CLK>,
> >+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> >+			clock-names = "aux", "cfg_ahb";
> >+
> >+			resets =  <&gcc GCC_USB0_PHY_BCR>,
> >+				 <&gcc GCC_USB3PHY_0_PHY_BCR>;
> >+			reset-names = "phy","common";
> >+			status = "disabled";
> >+
> >+			usb0_ssphy: phy@7d200 {
> >+				reg = <0x0007d200 0x130>,	/* tx */
> >+				      <0x0007d400 0x200>,	/* rx */
> >+				      <0x0007d800 0x1f8>,	/* pcs  */
> >+				      <0x0007d600 0x044>;	/* pcs misc */
> >+				#phy-cells = <0>;
> >+				clocks = <&gcc GCC_USB0_PIPE_CLK>;
> >+				clock-names = "pipe0";
> >+				clock-output-names = "usb0_pipe_clk";
> >+			};
> >+		};
> >+
> >+		usb3: usb3@8a00000 {
> >+			compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> >+			reg = <0x8af8800 0x400>;
> >+			#address-cells = <1>;
> >+			#size-cells = <1>;
> >+			ranges;
> >+
> >+			clocks = <&gcc GCC_SNOC_USB_CLK>,
> >+				 <&gcc GCC_ANOC_USB_AXI_CLK>,
> >+				 <&gcc GCC_USB0_MASTER_CLK>,
> >+				 <&gcc GCC_USB0_SLEEP_CLK>,
> >+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+
> >+			clock-names = "sys_noc_axi",
> >+				      "anoc_axi",
> >+				      "master",
> >+				      "sleep",
> >+				      "mock_utmi";
> >+
> >+			assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> >+					  <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+			assigned-clock-rates = <200000000>,
> >+					       <24000000>;
> >+
> >+			resets = <&gcc GCC_USB_BCR>;
> >+			status = "disabled";
> >+
> >+			dwc_0: usb@8a00000 {
> >+				compatible = "snps,dwc3";
> >+				reg = <0x8a00000 0xcd00>;
> >+				clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+				clock-names = "ref";
> >+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> >+				phys = <&qusb_phy_0>, <&usb0_ssphy>;
> >+				phy-names = "usb2-phy", "usb3-phy";
> >+				tx-fifo-resize;
> >+				snps,is-utmi-l1-suspend;
> >+				snps,hird-threshold = /bits/ 8 <0x0>;
> >+				snps,dis_u2_susphy_quirk;
> >+				snps,dis_u3_susphy_quirk;
> >+				dr_mode = "host";
> >+			};
> >+		};
> > 	};
> >
> > 	rpm-glink {
>
> --
> With best wishes
> Dmitry