From: Devi Priya <quic_devipriy@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <lpieralisi@kernel.org>,
<kw@linux.com>, <robh@kernel.org>, <bhelgaas@google.com>,
<krzysztof.kozlowski+dt@linaro.org>, <vkoul@kernel.org>,
<kishon@kernel.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <mani@kernel.org>, <p.zabel@pengutronix.de>,
<linus.walleij@linaro.org>, <linux-arm-msm@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-phy@lists.infradead.org>,
<linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>
Cc: <quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,
<quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,
<quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,
<quic_ipkumar@quicinc.com>
Subject: [PATCH V2 2/9] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks
Date: Tue, 4 Apr 2023 22:18:21 +0530 [thread overview]
Message-ID: <20230404164828.8031-3-quic_devipriy@quicinc.com> (raw)
In-Reply-To: <20230404164828.8031-1-quic_devipriy@quicinc.com>
Add the PCIe pipe clocks needed for enabling PCIe in IPQ9574
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Corrected the indentation for members of struct gcc_pcie1_pipe_clk
drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index ca40cb810a95..a4cf750043af 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -1522,6 +1522,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x28044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
.reg = 0x29064,
.clkr = {
@@ -1536,6 +1554,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x29044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie1_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
.reg = 0x2a064,
.clkr = {
@@ -1550,6 +1586,24 @@ static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie2_pipe_clk = {
+ .halt_reg = 0x2a044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2a044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie2_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie2_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
.reg = 0x2b064,
.clkr = {
@@ -1564,6 +1618,24 @@ static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
},
};
+static struct clk_branch gcc_pcie3_pipe_clk = {
+ .halt_reg = 0x2b044,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2b044,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data) {
+ .name = "gcc_pcie3_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &pcie3_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
F(24000000, P_XO, 1, 0, 0),
F(100000000, P_GPLL0, 8, 0, 0),
@@ -3878,9 +3950,13 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
+ [GCC_PCIE2_PIPE_CLK] = &gcc_pcie2_pipe_clk.clkr,
[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
+ [GCC_PCIE3_PIPE_CLK] = &gcc_pcie3_pipe_clk.clkr,
[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
--
2.17.1
next prev parent reply other threads:[~2023-04-04 16:49 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 16:48 [PATCH V2 0/9] Add PCIe support for IPQ9574 Devi Priya
2023-04-04 16:48 ` [PATCH V2 1/9] dt-bindings: clock: Add PCIe pipe clock definitions Devi Priya
2023-04-04 20:11 ` Stephen Boyd
2023-04-05 6:44 ` Krzysztof Kozlowski
2023-04-04 16:48 ` Devi Priya [this message]
2023-04-04 20:12 ` [PATCH V2 2/9] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks Stephen Boyd
2023-04-04 16:48 ` [PATCH V2 3/9] dt-bindings: phy: qcom,qmp-pcie: Add ipq9574 bindings Devi Priya
2023-04-05 6:46 ` Krzysztof Kozlowski
2023-04-05 6:49 ` Devi Priya
2023-04-04 16:48 ` [PATCH V2 4/9] phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs Devi Priya
2023-04-10 15:21 ` Vinod Koul
2023-04-10 15:23 ` Devi Priya
2023-04-04 16:48 ` [PATCH V2 5/9] dt-bindings: PCI: qcom: Add IPQ9574 Devi Priya
2023-04-05 6:58 ` Krzysztof Kozlowski
2023-04-11 10:57 ` Devi Priya
2023-04-11 11:52 ` Manivannan Sadhasivam
2023-04-11 14:00 ` Devi Priya
2023-04-04 16:48 ` [PATCH V2 6/9] dt-bindings: pinctrl: qcom: Add few missing functions Devi Priya
2023-04-05 6:58 ` Krzysztof Kozlowski
2023-04-10 6:34 ` Devi Priya
2023-04-04 16:48 ` [PATCH V2 7/9] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes Devi Priya
2023-04-04 16:48 ` [PATCH V2 8/9] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers Devi Priya
2023-04-04 16:48 ` [PATCH V2 9/9] PCI: qcom: Add support for IPQ9574 Devi Priya
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