From: Nitin Rawat <quic_nitirawa@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
konrad.dybcio@linaro.org, mani@kernel.org,
alim.akhtar@samsung.com, bvanassche@acm.org, avri.altman@wdc.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, cros-qcom-dts-watchers@chromium.org
Cc: linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Nitin Rawat <quic_nitirawa@quicinc.com>
Subject: [PATCH V4 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS
Date: Fri, 29 Sep 2023 18:49:36 +0530 [thread overview]
Message-ID: <20230929131936.29421-5-quic_nitirawa@quicinc.com> (raw)
In-Reply-To: <20230929131936.29421-1-quic_nitirawa@quicinc.com>
Align the binding property for clock such that "clocks" property
comes first followed by "clock-names" property.
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/ufs/qcom,ufs.yaml | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 802640efa956..d17bdc4e934f 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -295,14 +295,6 @@ examples:
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
- clock-names = "core_clk",
- "bus_aggr_clk",
- "iface_clk",
- "core_clk_unipro",
- "ref_clk",
- "tx_lane0_sync_clk",
- "rx_lane0_sync_clk",
- "rx_lane1_sync_clk";
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
@@ -311,6 +303,14 @@ examples:
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
freq-table-hz = <75000000 300000000>,
<0 0>,
<0 0>,
--
2.17.1
next prev parent reply other threads:[~2023-09-29 13:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-29 13:19 [PATCH V4 0/4] Add UFS host controller and Phy nodes for sc7280 Nitin Rawat
2023-09-29 13:19 ` [PATCH V4 1/4] scsi: ufs: qcom: dt-bindings: Add SC7280 compatible string Nitin Rawat
2023-09-30 14:43 ` Krzysztof Kozlowski
2023-09-29 13:19 ` [PATCH V4 2/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc Nitin Rawat
2023-09-29 13:25 ` Konrad Dybcio
2023-10-05 13:01 ` Luca Weiss
2023-09-29 13:19 ` [PATCH V4 3/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 IDP board Nitin Rawat
2023-09-29 13:26 ` Konrad Dybcio
2023-09-29 14:22 ` Nitin Rawat
2023-09-29 13:19 ` Nitin Rawat [this message]
2023-09-29 13:26 ` [PATCH V4 4/4] dt-bindings: ufs: qcom: Align clk binding property for Qualcomm UFS Konrad Dybcio
2023-09-30 14:45 ` Krzysztof Kozlowski
2023-09-29 13:27 ` [PATCH V4 0/4] Add UFS host controller and Phy nodes for sc7280 Konrad Dybcio
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