From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
cros-qcom-dts-watchers@chromium.org,
Rob Herring <robh@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH v2 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node
Date: Thu, 21 Mar 2024 16:46:21 +0530 [thread overview]
Message-ID: <20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org> (raw)
In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org>
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 39bd8f0eba1e..fe5485256b22 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2203,6 +2203,16 @@ pcie0: pcie@1c00000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie0_phy: phy@1c06000 {
@@ -2318,6 +2328,16 @@ pcie1: pcie@1c08000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie1_phy: phy@1c0e000 {
@@ -2433,6 +2453,16 @@ pcie2: pcie@1c10000 {
dma-coherent;
status = "disabled";
+
+ pcie@0 {
+ device_type = "pci";
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ bus-range = <0x01 0xff>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
};
pcie2_phy: phy@1c16000 {
--
2.25.1
next prev parent reply other threads:[~2024-03-21 11:16 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-21 11:16 [PATCH v2 00/21] Add PCIe bridge node in DT for Qcom SoCs Manivannan Sadhasivam
2024-03-21 11:16 ` Manivannan Sadhasivam [this message]
2024-03-21 11:16 ` [PATCH v2 02/21] arm64: dts: qcom: sdm845: Add PCIe bridge node Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 03/21] arm64: dts: qcom: sm8150: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 04/21] arm64: dts: qcom: sm8350: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 05/21] arm64: dts: qcom: sm8450: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 06/21] arm64: dts: qcom: sm8550: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 07/21] arm64: dts: qcom: sm8650: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 08/21] arm64: dts: qcom: sa8775p: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 09/21] arm64: dts: qcom: sc8280xp: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 10/21] arm64: dts: qcom: msm8998: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 11/21] arm64: dts: qcom: sc7280: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 12/21] arm64: dts: qcom: qcs404: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 13/21] arm64: dts: qcom: sc8180x: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 14/21] arm64: dts: qcom: msm8996: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 15/21] arm64: dts: qcom: ipq8074: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 16/21] arm64: dts: qcom: ipq6018: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 17/21] ARM: dts: qcom: ipq8064: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 18/21] ARM: dts: qcom: ipq4019: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 19/21] ARM: dts: qcom: apq8064: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 20/21] ARM: dts: qcom: sdx55: " Manivannan Sadhasivam
2024-03-21 11:16 ` [PATCH v2 21/21] arm64: dts: qcom: sm8650: Use "pcie" as the node name instead of "pci" Manivannan Sadhasivam
2024-03-23 0:11 ` [PATCH v2 00/21] Add PCIe bridge node in DT for Qcom SoCs Konrad Dybcio
2024-04-21 22:29 ` (subset) " Bjorn Andersson
2024-05-27 3:00 ` Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240321-pcie-qcom-bridge-dts-v2-1-1eb790c53e43@linaro.org \
--to=manivannan.sadhasivam@linaro.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=cros-qcom-dts-watchers@chromium.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).