From: abhinavk@codeaurora.org
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Jonathan Marek <jonathan@marek.ca>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
freedreno@lists.freedesktop.org
Subject: Re: [Freedreno] [PATCH v2 2/7] drm/msm/dpu: don't clear IRQ register twice
Date: Tue, 17 Aug 2021 20:11:15 -0700 [thread overview]
Message-ID: <237ec1051e5091ed300e6ccba9cea246@codeaurora.org> (raw)
In-Reply-To: <20210617222029.463045-3-dmitry.baryshkov@linaro.org>
On 2021-06-17 15:20, Dmitry Baryshkov wrote:
> We already clear the IRQ status register before processing IRQs, so do
> not clear the register again. Especially do not clear the IRQ status
> _after_ processing the IRQ as this way we can loose the event.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 17 -----------------
> 1 file changed, 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 2437b0c7c073..28e9b0d448db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] =
> {
> #define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
> #define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32))
>
> -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr
> *intr,
> - int irq_idx)
> -{
> - int reg_idx;
> -
> - if (!intr)
> - return;
> -
> - reg_idx = DPU_IRQ_REG(irq_idx);
> - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> DPU_IRQ_MASK(irq_idx));
> -
> - /* ensure register writes go through */
> - wmb();
> -}
> -
> /**
> * dpu_core_irq_callback_handler - dispatch core interrupts
> * @arg: private data of callback handler
> @@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms)
>
> dpu_core_irq_callback_handler(dpu_kms, irq_idx);
>
> - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx);
> -
> /*
> * When callback finish, clear the irq_status
> * with the matching mask. Once irq_status
next prev parent reply other threads:[~2021-08-18 3:11 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-17 22:20 [PARCH v2 0/7] drm/msm/dpu: merge dpu_core_irq into dpu_hw_interrupts Dmitry Baryshkov
2021-06-17 22:20 ` [PATCH v2 1/7] drm/msm/dpu: squash " Dmitry Baryshkov
2021-08-18 3:08 ` [Freedreno] " abhinavk
2021-06-17 22:20 ` [PATCH v2 2/7] drm/msm/dpu: don't clear IRQ register twice Dmitry Baryshkov
2021-08-18 3:11 ` abhinavk [this message]
2021-06-17 22:20 ` [PATCH v2 3/7] drm/msm/dpu: merge struct dpu_irq into struct dpu_hw_intr Dmitry Baryshkov
2021-08-18 3:20 ` [Freedreno] " abhinavk
2021-06-17 22:20 ` [PATCH v2 4/7] drm/msm/dpu: allow just single IRQ callback Dmitry Baryshkov
2021-08-18 3:30 ` [Freedreno] " abhinavk
2022-01-19 0:10 ` abhinavk
2022-02-01 4:02 ` Dmitry Baryshkov
2021-06-17 22:20 ` [PATCH v2 5/7] drm/msm/dpu: remove extra wrappers around dpu_core_irq Dmitry Baryshkov
2021-08-18 3:30 ` [Freedreno] " abhinavk
2021-06-17 22:20 ` [PATCH v2 6/7] drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq Dmitry Baryshkov
2021-08-18 3:35 ` [Freedreno] " abhinavk
2021-06-17 22:20 ` [PATCH v2 7/7] drm/msm/dpu: remove struct dpu_encoder_irq and enum dpu_intr_idx Dmitry Baryshkov
2021-08-18 3:40 ` [Freedreno] " abhinavk
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