From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B087C4338F for ; Wed, 18 Aug 2021 03:11:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2E3860E78 for ; Wed, 18 Aug 2021 03:11:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234435AbhHRDLv (ORCPT ); Tue, 17 Aug 2021 23:11:51 -0400 Received: from m43-7.mailgun.net ([69.72.43.7]:61296 "EHLO m43-7.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231449AbhHRDLu (ORCPT ); Tue, 17 Aug 2021 23:11:50 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1629256276; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=W6ljQtKKhBtKysS8ZErAoZ1I7F5yu9ez4L8hDRonFew=; b=bw60McKwE/rusmZHkfgE+hY4wQWj1oyr853Rvf+UBhHzwH/+UDFAYaYyNo+LWrnWJPuF3QNU qK3umJUJAhSAwMK2c+ItP8TPTcdcEFA77oD8oBqh1fwvOvxDzOzr9F9SxEvJFsA+i0e+gXv4 0RA8QTKo6cnONvlI8xbcBiMwC0U= X-Mailgun-Sending-Ip: 69.72.43.7 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-west-2.postgun.com with SMTP id 611c7a54454b7a558f54030a (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 18 Aug 2021 03:11:16 GMT Sender: abhinavk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 21548C43617; Wed, 18 Aug 2021 03:11:16 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: abhinavk) by smtp.codeaurora.org (Postfix) with ESMTPSA id 3C8E2C4338F; Wed, 18 Aug 2021 03:11:15 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Tue, 17 Aug 2021 20:11:15 -0700 From: abhinavk@codeaurora.org To: Dmitry Baryshkov Cc: Bjorn Andersson , Rob Clark , Sean Paul , Jonathan Marek , Stephen Boyd , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , Daniel Vetter , freedreno@lists.freedesktop.org Subject: Re: [Freedreno] [PATCH v2 2/7] drm/msm/dpu: don't clear IRQ register twice In-Reply-To: <20210617222029.463045-3-dmitry.baryshkov@linaro.org> References: <20210617222029.463045-1-dmitry.baryshkov@linaro.org> <20210617222029.463045-3-dmitry.baryshkov@linaro.org> Message-ID: <237ec1051e5091ed300e6ccba9cea246@codeaurora.org> X-Sender: abhinavk@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2021-06-17 15:20, Dmitry Baryshkov wrote: > We already clear the IRQ status register before processing IRQs, so do > not clear the register again. Especially do not clear the IRQ status > _after_ processing the IRQ as this way we can loose the event. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar > --- > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 17 ----------------- > 1 file changed, 17 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index 2437b0c7c073..28e9b0d448db 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -120,21 +120,6 @@ static const struct dpu_intr_reg dpu_intr_set[] = > { > #define DPU_IRQ_REG(irq_idx) (irq_idx / 32) > #define DPU_IRQ_MASK(irq_idx) (BIT(irq_idx % 32)) > > -static void dpu_hw_intr_clear_intr_status_nolock(struct dpu_hw_intr > *intr, > - int irq_idx) > -{ > - int reg_idx; > - > - if (!intr) > - return; > - > - reg_idx = DPU_IRQ_REG(irq_idx); > - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, > DPU_IRQ_MASK(irq_idx)); > - > - /* ensure register writes go through */ > - wmb(); > -} > - > /** > * dpu_core_irq_callback_handler - dispatch core interrupts > * @arg: private data of callback handler > @@ -203,8 +188,6 @@ irqreturn_t dpu_core_irq(struct dpu_kms *dpu_kms) > > dpu_core_irq_callback_handler(dpu_kms, irq_idx); > > - dpu_hw_intr_clear_intr_status_nolock(intr, irq_idx); > - > /* > * When callback finish, clear the irq_status > * with the matching mask. Once irq_status