From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB64AC4332F for ; Thu, 6 Oct 2022 01:06:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229807AbiJFBGw (ORCPT ); Wed, 5 Oct 2022 21:06:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229639AbiJFBGv (ORCPT ); Wed, 5 Oct 2022 21:06:51 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF4EDCE00; Wed, 5 Oct 2022 18:06:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1665018410; x=1696554410; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=QZ5ahBjjXRi+rjFDpA2pvp9EwPYIwHpkOVJpXhPj5KE=; b=YzSTheDWU5+4+a3Od08RiGRKh5yr6s7pF71WLeZIzUtaKZfzs1GfXTBq Tg+2Qi7nxpOB+CF+jEYoGxeUztpMu5OhEXDsIEwm3LxJ0QvWQgM/wnEJc U1YUvEvqj3p8U8cPU/xqmwJhCHuBgHB6a8lTzcPNeOpoSfWdqg9BhU757 s=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 05 Oct 2022 18:06:50 -0700 X-QCInternal: smtphost Received: from unknown (HELO nasanex01a.na.qualcomm.com) ([10.52.223.231]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2022 18:06:50 -0700 Received: from asutoshd-linux1.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 5 Oct 2022 18:06:49 -0700 From: Asutosh Das To: , , , , , CC: Asutosh Das , , , , , , , Subject: [PATCH v2 03/17] ufs: core: Introduce Multi-circular queue capability Date: Wed, 5 Oct 2022 18:06:02 -0700 Message-ID: <2708bc000c388cc784d500f28997d7df93f8259f.1665017636.git.quic_asutoshd@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support to check for MCQ capability in the UFSHC. This capability can be used by host drivers to control MCQ enablement. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Asutosh Das --- drivers/ufs/core/ufshcd.c | 4 ++++ include/ufs/ufshcd.h | 13 +++++++++++++ 2 files changed, 17 insertions(+) diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c index e2be3f4..8d93797 100644 --- a/drivers/ufs/core/ufshcd.c +++ b/drivers/ufs/core/ufshcd.c @@ -2250,6 +2250,10 @@ static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) if (err) dev_err(hba->dev, "crypto setup failed\n"); + hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); + if (!hba->mcq_sup) + return err; + hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, hba->mcq_capabilities); diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index da1eb8a..da7ec0c 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -660,6 +660,12 @@ enum ufshcd_caps { * notification if it is supported by the UFS device. */ UFSHCD_CAP_TEMP_NOTIF = 1 << 11, + + /* + * This capability allows the host controller driver to turn on/off + * MCQ mode. MCQ mode may be used to increase performance. + */ + UFSHCD_CAP_MCQ_EN = 1 << 12, }; struct ufs_hba_variant_params { @@ -820,6 +826,7 @@ struct ufs_hba_monitor { * @complete_put: whether or not to call ufshcd_rpm_put() from inside * ufshcd_resume_complete() * @ext_iid_sup: is EXT_IID is supported by UFSHC + * @mcq_sup: is mcq supported by UFSHC */ struct ufs_hba { void __iomem *mmio_base; @@ -969,8 +976,14 @@ struct ufs_hba { u32 luns_avail; bool complete_put; bool ext_iid_sup; + bool mcq_sup; }; +static inline bool is_mcq_supported(struct ufs_hba *hba) +{ + return hba->mcq_sup && (hba->caps & UFSHCD_CAP_MCQ_EN); +} + /* Returns true if clocks can be gated. Otherwise false */ static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) { -- 2.7.4