From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
iommu@lists.linux-foundation.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Doug Anderson <dianders@chromium.org>,
Krishna Reddy <vdumpa@nvidia.com>,
Thierry Reding <treding@nvidia.com>,
Tomasz Figa <tfiga@chromium.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Subject: Re: [PATCHv4] iommu/arm-smmu: Optimize ->tlb_flush_walk() for qcom implementation
Date: Wed, 11 Aug 2021 16:23:16 +0530 [thread overview]
Message-ID: <47c50d2010a0c8f9c21c20584fb8db5e@codeaurora.org> (raw)
In-Reply-To: <20210811103011.GD4426@willie-the-truck>
On 2021-08-11 16:00, Will Deacon wrote:
> On Wed, Aug 11, 2021 at 11:37:25AM +0530, Sai Prakash Ranjan wrote:
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> index f7da8953afbe..3904b598e0f9 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> @@ -327,9 +327,16 @@ static void arm_smmu_tlb_inv_range_s2(unsigned
>> long iova, size_t size,
>> static void arm_smmu_tlb_inv_walk_s1(unsigned long iova, size_t size,
>> size_t granule, void *cookie)
>> {
>> - arm_smmu_tlb_inv_range_s1(iova, size, granule, cookie,
>> - ARM_SMMU_CB_S1_TLBIVA);
>> - arm_smmu_tlb_sync_context(cookie);
>> + struct arm_smmu_domain *smmu_domain = cookie;
>> + struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
>> +
>> + if (cfg->flush_walk_prefer_tlbiasid) {
>> + arm_smmu_tlb_inv_context_s1(cookie);
>
> Hmm, this introduces an unconditional wmb() if tlbiasid is preferred. I
> think that should be predicated on ARM_SMMU_FEAT_COHERENT_WALK like it
> is
> for the by-VA ops. Worth doing as a separate patch.
>
Ok I will keep this as-is for now then.
>> + } else {
>> + arm_smmu_tlb_inv_range_s1(iova, size, granule, cookie,
>> + ARM_SMMU_CB_S1_TLBIVA);
>> + arm_smmu_tlb_sync_context(cookie);
>> + }
>> }
>>
>> static void arm_smmu_tlb_add_page_s1(struct iommu_iotlb_gather
>> *gather,
>> @@ -765,8 +772,10 @@ static int arm_smmu_init_domain_context(struct
>> iommu_domain *domain,
>> .iommu_dev = smmu->dev,
>> };
>>
>> - if (!iommu_get_dma_strict(domain))
>> + if (!iommu_get_dma_strict(domain)) {
>> pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT;
>> + cfg->flush_walk_prefer_tlbiasid = true;
>
> This is going to interact badly with Robin's series to allow dynamic
> transition to non-strict mode, as we don't have a mechanism to switch
> over to the by-ASID behaviour. Yes, it should _work_, but it's ugly
> having
> different TLBI behaviour just because of the how the domain became
> non-strict.
>
> Robin -- I think this originated from your idea at [1]. Any idea how to
> make
> it work with your other series, or shall we drop this part for now and
> leave
> the TLB invalidation behaviour the same for now?
>
> Will
>
> [1]
> https://lore.kernel.org/r/da62ff1c-9b49-34d3-69a1-1a674e4a30f7@arm.com
Right, I think we can drop this non-strict change for now because it
also makes
it a pain to backport it to 5.4/5.10 kernels because of large number of
changes
in dma apis in recent kernels. I will let you and Robin decide if it's
ok to
drop this change and introduce it later with a different patch.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2021-08-11 10:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-11 6:07 [PATCHv4] iommu/arm-smmu: Optimize ->tlb_flush_walk() for qcom implementation Sai Prakash Ranjan
2021-08-11 10:30 ` Will Deacon
2021-08-11 10:53 ` Sai Prakash Ranjan [this message]
2021-08-11 15:53 ` Robin Murphy
2021-08-11 16:06 ` Sai Prakash Ranjan
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