From: hongwus@codeaurora.org
To: Can Guo <cang@codeaurora.org>
Cc: asutoshd@codeaurora.org, nguyenb@codeaurora.org,
rnayak@codeaurora.org, linux-scsi@vger.kernel.org,
kernel-team@android.com, saravanak@google.com,
salyzyn@google.com, Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Avri Altman <avri.altman@wdc.com>,
"James E.J. Bottomley" <jejb@linux.ibm.com>,
"Martin K. Petersen" <martin.petersen@oracle.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 7/8] scsi: ufs-qcom: Delay specific time before gate ref clk
Date: Wed, 05 Feb 2020 15:20:10 +0800 [thread overview]
Message-ID: <537a8695bcadd7d5686a6b6e3c04f2af@codeaurora.org> (raw)
In-Reply-To: <1580721472-10784-8-git-send-email-cang@codeaurora.org>
On 2020-02-03 17:17, Can Guo wrote:
> After enter hibern8, as UFS JEDEC ver 3.0 requires, a specific gating
> wait
> time is required before disable the device reference clock. If it is
> not
> specified, use the old delay.
>
> Signed-off-by: Can Guo <cang@codeaurora.org>
> Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>
> ---
> drivers/scsi/ufs/ufs-qcom.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
> index 85d7c17..3b5b2d9 100644
> --- a/drivers/scsi/ufs/ufs-qcom.c
> +++ b/drivers/scsi/ufs/ufs-qcom.c
> @@ -833,6 +833,8 @@ static int ufs_qcom_bus_register(struct
> ufs_qcom_host *host)
>
> static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool
> enable)
> {
> + unsigned long gating_wait;
> +
> if (host->dev_ref_clk_ctrl_mmio &&
> (enable ^ host->is_dev_ref_clk_enabled)) {
> u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
> @@ -845,11 +847,16 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct
> ufs_qcom_host *host, bool enable)
> /*
> * If we are here to disable this clock it might be immediately
> * after entering into hibern8 in which case we need to make
> - * sure that device ref_clk is active at least 1us after the
> + * sure that device ref_clk is active for specific time after
> * hibern8 enter.
> */
> - if (!enable)
> - udelay(1);
> + if (!enable) {
> + gating_wait = host->hba->dev_info.clk_gating_wait_us;
> + if (!gating_wait)
> + udelay(1);
> + else
> + usleep_range(gating_wait, gating_wait + 10);
> + }
>
> writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio);
Reviewed-by: Hongwu Su <hongwus@codeaurora.org>
prev parent reply other threads:[~2020-02-05 7:20 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1580721472-10784-1-git-send-email-cang@codeaurora.org>
2020-02-03 9:17 ` [PATCH v5 4/8] scsi: ufs-qcom: Adjust bus bandwidth voting and unvoting Can Guo
2020-02-05 2:17 ` Asutosh Das (asd)
2020-02-03 9:17 ` [PATCH v5 7/8] scsi: ufs-qcom: Delay specific time before gate ref clk Can Guo
2020-02-05 7:20 ` hongwus [this message]
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