From: okukatla@codeaurora.org
To: Stephen Boyd <swboyd@chromium.org>
Cc: Andy Gross <agross@kernel.org>, Georgi Djakov <djakov@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Sibi Sankar <sibis@codeaurora.org>,
bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
evgreen@google.com, georgi.djakov@linaro.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, seansw@qti.qualcomm.com,
elder@linaro.org, linux-arm-msm-owner@vger.kernel.org
Subject: Re: [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
Date: Mon, 09 Aug 2021 22:01:46 +0530 [thread overview]
Message-ID: <618b3a664b3556718a867e815e94578f@codeaurora.org> (raw)
In-Reply-To: <CAE-0n51btkt9ehEFrm+WucP90ZufKw1PEQqzNGVDRy51jByXkw@mail.gmail.com>
Thanks Stephen for the reviews!
On 2021-07-09 04:52, Stephen Boyd wrote:
> Quoting Odelu Kukatla (2021-06-18 04:28:52)
>> Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280
>> SoCs.
>>
>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
>> ---
>> .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9
>> ++++++++-
>> include/dt-bindings/interconnect/qcom,osm-l3.h | 10
>> +++++++++-
>> 2 files changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> index d6a95c3..9f67c8e 100644
>> --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
>> @@ -18,12 +18,19 @@ properties:
>> compatible:
>> enum:
>> - qcom,sc7180-osm-l3
>> + - qcom,sc7280-epss-l3
>> - qcom,sdm845-osm-l3
>> - qcom,sm8150-osm-l3
>> - qcom,sm8250-epss-l3
>>
>> reg:
>> - maxItems: 1
>> + minItems: 1
>> + maxItems: 4
>
> Can we base this on the compatible string so that only sc7280-epss-l3
> requires 4 items? and then the others require 1 reg property?
>
Done, Addressing this in new revision.
>> + items:
>> + - description: OSM clock domain-0 base address and size
>> + - description: OSM clock domain-1 base address and size
>> + - description: OSM clock domain-2 base address and size
>> + - description: OSM clock domain-3 base address and size
>>
>> clocks:
>> items:
next prev parent reply other threads:[~2021-08-09 16:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-18 11:28 [V4 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-06-18 11:28 ` [V4 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-07-08 23:22 ` Stephen Boyd
2021-08-09 16:31 ` okukatla [this message]
2021-06-18 11:28 ` [V4 2/3] interconnect: qcom: Add EPSS L3 support " Odelu Kukatla
2021-07-08 23:21 ` Stephen Boyd
2021-08-09 16:45 ` okukatla
2021-06-18 11:28 ` [V4 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-07-08 23:04 ` Stephen Boyd
2021-08-09 16:47 ` okukatla
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