From: Christian Marangi <ansuelsmth@gmail.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: Robert Marko <robimarko@gmail.com>,
rafael@kernel.org, viresh.kumar@linaro.org, agross@kernel.org,
andersson@kernel.org, ilia.lin@kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-msm@vger.kernel.org
Subject: Re: [RESEND PATCH v2 2/2] cpufreq: qcom-nvmem: add support for IPQ8064
Date: Wed, 31 May 2023 03:40:00 +0200 [thread overview]
Message-ID: <647709b8.df0a0220.28e58.6a42@mx.google.com> (raw)
In-Reply-To: <507831fd-326a-a5f7-cdc1-5584ad1aa11b@linaro.org>
On Wed, May 31, 2023 at 10:40:54AM +0200, Konrad Dybcio wrote:
>
>
> On 30.05.2023 18:58, Robert Marko wrote:
> > From: Christian Marangi <ansuelsmth@gmail.com>
> >
> > IPQ8064 comes in 3 families:
> > * IPQ8062 up to 1.0GHz
> > * IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz
> > * IPQ8065/IPQ8069 up to 1.7Ghz
> >
> > So, in order to be able to share one OPP table, add support for
> > IPQ8064 family based of SMEM SoC ID-s as speedbin fuse is always 0 on
> > IPQ8064.
> >
> > Bit are set with the following logic:
> > * IPQ8062 BIT 0
> > * IPQ8064/IPQ8066/IPQ8068 BIT 1
> > * IPQ8065/IPQ8069 BIT 2
> >
> > speed is never fused, only psv values are fused.
> > Set speed to the versions to permit a unified opp table following
> > this named opp:
> >
> > opp-microvolt-speed<SPEED_VALUE>-pvs<PSV_VALUE>-v0
> >
> > Example:
> > - for ipq8062 psv2
> > opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>
> > - for ipq8064 psv2
> > opp-microvolt-speed2-pvs2-v0 = <925000 878750 971250>;
> > - for ipq8065 psv2
> > opp-microvolt-speed4-pvs2-v0 = <950000 902500 997500>;
> >
> > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> > Signed-off-by: Robert Marko <robimarko@gmail.com>
> > ---
> > drivers/cpufreq/qcom-cpufreq-nvmem.c | 73 +++++++++++++++++++++++++++-
> > 1 file changed, 72 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > index ce444b5962f2..c644138680ba 100644
> > --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> > @@ -34,6 +34,10 @@
> > #define IPQ8074_HAWKEYE_VERSION BIT(0)
> > #define IPQ8074_ACORN_VERSION BIT(1)
> >
> > +#define IPQ8062_VERSION BIT(0)
> > +#define IPQ8064_VERSION BIT(1)
> > +#define IPQ8065_VERSION BIT(2)
> > +
> > struct qcom_cpufreq_drv;
> >
> > struct qcom_cpufreq_match_data {
> > @@ -207,6 +211,69 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
> > return ret;
> > }
> >
> > +static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev,
> > + struct nvmem_cell *speedbin_nvmem,
> > + char **pvs_name,
> > + struct qcom_cpufreq_drv *drv)
> > +{
> > + int speed = 0, pvs = 0, pvs_ver = 0;
> > + int msm_id, ret = 0;
> > + u8 *speedbin;
> > + size_t len;
> > +
> > + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> > +
> > + if (IS_ERR(speedbin))
> > + return PTR_ERR(speedbin);
> > +
> > + switch (len) {
> Do we expect more variety here? Otherwise a switch statement sounds a
> bit too heavy for the job, imo.
>
Well no, considering ipq8064 is effectively EOL i guess format 4 is the
only one present. But if you check the driver this is like a pattern so
the idea was too keep that. I can totally change that to a simple
if (len != 4) if we really want.
> > + case 4:
> > + get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
> > + speedbin);
> > + break;
> > + default:
> > + dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
> > + ret = -ENODEV;
> > + goto len_error;
> > + }
> > +
> > + ret = qcom_smem_get_soc_id(&msm_id);
> > + if (ret)
> > + return ret;
> > +
> > + switch (msm_id) {
> > + case QCOM_ID_IPQ8062:
> > + drv->versions = IPQ8062_VERSION;
> > + break;
> > + case QCOM_ID_IPQ8064:
> > + case QCOM_ID_IPQ8066:
> > + case QCOM_ID_IPQ8068:
> > + drv->versions = IPQ8064_VERSION;
> > + break;
> > + case QCOM_ID_IPQ8065:
> > + case QCOM_ID_IPQ8069:
> > + drv->versions = IPQ8065_VERSION;
> > + break;
> > + default:
> > + dev_err(cpu_dev,
> > + "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n",
> > + msm_id);
> > + drv->versions = IPQ8062_VERSION;
> > + break;
> > + }
> > +
> > + /*
> > + * IPQ8064 speed is never fused. Only psv values are fused.
> > + * Set speed to the versions to permit a unified opp table.
> > + */
> > + snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
> > + drv->versions, pvs, pvs_ver);
> > +
> > +len_error:
> > + kfree(speedbin);
> Perhaps we should switch to devres-managed nvmem soon..
>
devres nvmem would be very good, maybe an idea would be search for the
actualy use of nvmem_cell_read and see if it's worth to introduce these
new API.
> > + return ret;
> > +}
> > +
> > static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
> > struct nvmem_cell *speedbin_nvmem,
> > char **pvs_name,
> > @@ -256,6 +323,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = {
> > .genpd_names = qcs404_genpd_names,
> > };
> >
> > +static const struct qcom_cpufreq_match_data match_data_ipq8064 = {
> > + .get_version = qcom_cpufreq_ipq8064_name_version,
> > +};
> > +
> > static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
> > .get_version = qcom_cpufreq_ipq8074_name_version,
> > };
> > @@ -404,7 +475,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
> > { .compatible = "qcom,apq8096", .data = &match_data_kryo },
> > { .compatible = "qcom,msm8996", .data = &match_data_kryo },
> > { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
> > - { .compatible = "qcom,ipq8064", .data = &match_data_krait },
> > + { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 },
> > { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
> > { .compatible = "qcom,apq8064", .data = &match_data_krait },
> > { .compatible = "qcom,msm8974", .data = &match_data_krait },
--
Ansuel
next prev parent reply other threads:[~2023-05-31 8:48 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 16:58 [RESEND PATCH v2 1/2] cpufreq: qcom-nvmem: add support for IPQ8074 Robert Marko
2023-05-30 16:58 ` [RESEND PATCH v2 2/2] cpufreq: qcom-nvmem: add support for IPQ8064 Robert Marko
2023-05-31 2:03 ` Dmitry Baryshkov
2023-05-31 1:36 ` Christian Marangi
2023-06-01 15:07 ` Dmitry Baryshkov
2023-06-09 14:20 ` Christian Marangi
2023-06-09 14:53 ` Dmitry Baryshkov
2023-06-09 15:02 ` Christian Marangi
2023-06-09 16:17 ` Dmitry Baryshkov
2023-05-31 8:40 ` Konrad Dybcio
2023-05-31 1:40 ` Christian Marangi [this message]
2023-05-31 2:08 ` [RESEND PATCH v2 1/2] cpufreq: qcom-nvmem: add support for IPQ8074 Dmitry Baryshkov
2023-06-01 12:55 ` Kathiravan T
2023-06-01 13:08 ` Konrad Dybcio
2023-06-01 13:10 ` Robert Marko
2023-06-01 13:24 ` Kathiravan T
2023-06-01 14:49 ` Kathiravan T
2023-06-01 14:55 ` Robert Marko
2023-06-02 8:57 ` Konrad Dybcio
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=647709b8.df0a0220.28e58.6a42@mx.google.com \
--to=ansuelsmth@gmail.com \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=ilia.lin@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rafael@kernel.org \
--cc=robimarko@gmail.com \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).