From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>
Cc: coresight@lists.linaro.org, Stephen Boyd <swboyd@chromium.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, denik@google.com,
leo.yan@linaro.org, peterz@infradead.org,
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCH 2/2] coresight: etb10: Fix possible NULL ptr dereference in etb_enable_perf()
Date: Wed, 7 Oct 2020 18:30:25 +0530 [thread overview]
Message-ID: <6f10c09e130ff241c728c40840f7aa67fdc1b737.1602074787.git.saiprakash.ranjan@codeaurora.org> (raw)
In-Reply-To: <cover.1602074787.git.saiprakash.ranjan@codeaurora.org>
There was a report of NULL pointer dereference in ETF enable
path for perf CS mode with PID monitoring. It is almost 100%
reproducible when the process to monitor is something very
active such as chrome and with ETF as the sink, not ETR.
But code path shows that ETB has a similar path as ETF, so
there could be possible NULL pointer dereference crash in
ETB as well. Currently in a bid to find the pid, the owner
is dereferenced via task_pid_nr() call in etb_enable_perf()
and with owner being NULL, we can get a NULL pointer
dereference, so have a similar fix as ETF where we cache PID
in alloc_buffer() callback which is called as the part of
etm_setup_aux().
Fixes: 75d7dbd38824 ("coresight: etb10: Add support for CPU-wide trace scenarios")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
drivers/hwtracing/coresight/coresight-etb10.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 248cc82c838e..1b320ab581ca 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -176,6 +176,7 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data)
unsigned long flags;
struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct perf_output_handle *handle = data;
+ struct cs_buffers *buf = etm_perf_sink_config(handle);
spin_lock_irqsave(&drvdata->spinlock, flags);
@@ -186,7 +187,7 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data)
}
/* Get a handle on the pid of the process to monitor */
- pid = task_pid_nr(handle->event->owner);
+ pid = buf->pid;
if (drvdata->pid != -1 && drvdata->pid != pid) {
ret = -EBUSY;
@@ -383,6 +384,7 @@ static void *etb_alloc_buffer(struct coresight_device *csdev,
if (!buf)
return NULL;
+ buf->pid = task_pid_nr(event->owner);
buf->snapshot = overwrite;
buf->nr_pages = nr_pages;
buf->data_pages = pages;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-10-07 13:01 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 13:00 [PATCH 0/2] coresight: etf/etb: NULL Pointer dereference crash fixes Sai Prakash Ranjan
2020-10-07 13:00 ` [PATCH 1/2] coresight: tmc-etf: Fix NULL ptr dereference in tmc_enable_etf_sink_perf() Sai Prakash Ranjan
2020-10-13 16:35 ` Suzuki K Poulose
2020-10-14 7:50 ` Sai Prakash Ranjan
2020-10-14 9:36 ` Sai Prakash Ranjan
2020-10-14 13:16 ` Suzuki K Poulose
2020-10-14 15:59 ` Sai Prakash Ranjan
2020-10-20 16:10 ` Sai Prakash Ranjan
2020-10-21 7:29 ` Sai Prakash Ranjan
2020-10-21 10:08 ` Suzuki Poulose
2020-10-22 8:02 ` Sai Prakash Ranjan
2020-10-22 9:27 ` Suzuki Poulose
2020-10-22 11:07 ` Sai Prakash Ranjan
2020-10-22 11:14 ` Suzuki Poulose
2020-10-22 11:20 ` Sai Prakash Ranjan
2020-10-07 13:00 ` Sai Prakash Ranjan [this message]
2020-12-29 20:15 ` [PATCH 0/2] coresight: etf/etb: NULL Pointer dereference crash fixes patchwork-bot+linux-arm-msm
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