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From: Jonathan Marek <jonathan@marek.ca>
To: linux-arm-msm@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
	Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
	Daniel Vetter <daniel@ffwll.ch>, Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Georgi Djakov <georgi.djakov@linaro.org>,
	kbuild test robot <lkp@intel.com>,
	open list <linux-kernel@vger.kernel.org>,
	"open list:DRM DRIVER FOR MSM ADRENO GPU" 
	<dri-devel@lists.freedesktop.org>,
	"open list:DRM DRIVER FOR MSM ADRENO GPU" 
	<freedreno@lists.freedesktop.org>,
	"open list:INTERCONNECT API" <linux-pm@vger.kernel.org>
Subject: Re: [RFC PATCH] interconnect: qcom: add functions to query addr/cmds for a path
Date: Wed, 1 Jul 2020 13:03:48 -0400
Message-ID: <7c1f9635-f4d5-a977-905d-3d7cc9d74ec2@marek.ca> (raw)
In-Reply-To: <20200701165628.GA19996@jcrouse1-lnx.qualcomm.com>

On 7/1/20 12:56 PM, Jordan Crouse wrote:
> On Wed, Jul 01, 2020 at 12:25:25AM -0400, Jonathan Marek wrote:
>> The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able
>> to query the interconnect driver for bcm addresses and commands.
>>
>> I'm not sure what is the best way to go about implementing this, this is
>> what I came up with.
>>
>> I included a quick example of how this can be used by the a6xx driver to
>> fill out the GMU bw_table (two ddr bandwidth levels in this example, note
>> this would be using the frequency table in dts and not hardcoded values).
> 
> I would like to add my enthusiasm for this idea but I'm not much of an
> interconnect or RPMh expert so I would defer to them to be sure that the APIs
> are robust enough to cover all the corner cases.
> 
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 20 ++++-------
>>   drivers/interconnect/qcom/icc-rpmh.c  | 50 +++++++++++++++++++++++++++
>>   include/soc/qcom/icc.h                | 11 ++++++
>>   3 files changed, 68 insertions(+), 13 deletions(-)
>>   create mode 100644 include/soc/qcom/icc.h
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
>> index ccd44d0418f8..1fb8f0480be3 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
>> @@ -4,6 +4,7 @@
>>   #include <linux/completion.h>
>>   #include <linux/circ_buf.h>
>>   #include <linux/list.h>
>> +#include <soc/qcom/icc.h>
>>   
>>   #include "a6xx_gmu.h"
>>   #include "a6xx_gmu.xml.h"
>> @@ -320,24 +321,18 @@ static void a640_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
>>   	msg->cnoc_cmds_data[1][2] =  0x60000001;
>>   }
>>   
>> -static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
>> +static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg, struct icc_path *path)
>>   {
>>   	/*
>>   	 * Send a single "off" entry just to get things running
>>   	 * TODO: bus scaling
>>   	 */
>> -	msg->bw_level_num = 1;
>> -
>> -	msg->ddr_cmds_num = 3;
>> +	msg->bw_level_num = 2;
>>   	msg->ddr_wait_bitmask = 0x01;
> 
> We're going to need a API function for the wait bitmask too.
>   
>> -	msg->ddr_cmds_addrs[0] = 0x50000;
>> -	msg->ddr_cmds_addrs[1] = 0x50004;
>> -	msg->ddr_cmds_addrs[2] = 0x5007c;
>> -
>> -	msg->ddr_cmds_data[0][0] =  0x40000000;
>> -	msg->ddr_cmds_data[0][1] =  0x40000000;
>> -	msg->ddr_cmds_data[0][2] =  0x40000000;
>> +	msg->ddr_cmds_num = qcom_icc_query_addr(path, msg->ddr_cmds_addrs);
>> +	qcom_icc_query_cmd(path, msg->ddr_cmds_data[0], 0, 0);
>> +	qcom_icc_query_cmd(path, msg->ddr_cmds_data[1], 0, 7216000);
>>   
>>   	/*
>>   	 * These are the CX (CNOC) votes - these are used by the GMU but the
>> @@ -388,7 +383,6 @@ static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
>>   	msg->cnoc_cmds_data[1][2] =  0x60000001;
>>   }
>>   
>> -
>>   static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
>>   {
>>   	struct a6xx_hfi_msg_bw_table msg = { 0 };
>> @@ -400,7 +394,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
>>   	else if (adreno_is_a640(adreno_gpu))
>>   		a640_build_bw_table(&msg);
>>   	else if (adreno_is_a650(adreno_gpu))
>> -		a650_build_bw_table(&msg);
>> +		a650_build_bw_table(&msg, adreno_gpu->base.icc_path);
>>   	else
>>   		a6xx_build_bw_table(&msg);
>>   
>> diff --git a/drivers/interconnect/qcom/icc-rpmh.c b/drivers/interconnect/qcom/icc-rpmh.c
>> index 3ac5182c9ab2..3ce2920330f9 100644
>> --- a/drivers/interconnect/qcom/icc-rpmh.c
>> +++ b/drivers/interconnect/qcom/icc-rpmh.c
>> @@ -9,6 +9,7 @@
>>   
>>   #include "bcm-voter.h"
>>   #include "icc-rpmh.h"
>> +#include "../internal.h"
>>   
>>   /**
>>    * qcom_icc_pre_aggregate - cleans up stale values from prior icc_set
>> @@ -92,6 +93,55 @@ int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
>>   }
>>   EXPORT_SYMBOL_GPL(qcom_icc_set);
>>   
>> +static u32 bcm_query(struct qcom_icc_bcm *bcm, u64 sum_avg, u64 max_peak)
>> +{
>> +	u64 temp, agg_peak = 0;
>> +	int i;
>> +
>> +	for (i = 0; i < bcm->num_nodes; i++) {
>> +		temp = max_peak * bcm->aux_data.width;
>> +		do_div(temp, bcm->nodes[i]->buswidth);
>> +		agg_peak = max(agg_peak, temp);
>> +	}
>> +
>> +	temp = agg_peak * 1000ULL;
>> +	do_div(temp, bcm->aux_data.unit);
>> +
>> +	// TODO vote_x
>> +
>> +	return BCM_TCS_CMD(true, temp != 0, 0, temp);
>> +}
>> +
>> +int qcom_icc_query_addr(struct icc_path *path, u32 *addr)
> 
> The leaf driver won't know the size of the path, so we'll likely need to kmalloc
> and return the array or allow addr to be NULL and have the leaf driver do the
> allocation itself once it knows what k is.
> 

In the a6xx gpu case, the a6xx_hfi_msg_bw_table has a fixed array size 
(allows up to 8 commands for ddr and 6 for cnoc), so there shouldn't be 
a need for any allocation.

Allowing addr to be NULL to get the # of addrs/cmds (so the a6xx driver 
can bail out if it can't fit, although that should never happen) would 
be OK (or having an array size parameter so the function can return an 
error), but IMO not needed for the "qcom_icc_query_cmd" function below, 
since it returns the same number of commands the "qcom_icc_query_addr" 
returns addresses.

>> +{
>> +	struct qcom_icc_node *qn;
>> +	int i, j, k = 0;
>> +
>> +	for (i = 0; i < path->num_nodes; i++) {
>> +		qn = path->reqs[i].node->data;
>> +		for (j = 0; j < qn->num_bcms; j++, k++)
>> +			addr[k] = qn->bcms[j]->addr;
>> +	}
>> +
>> +	return k;
>> +}
>> +EXPORT_SYMBOL_GPL(qcom_icc_query_addr);
>> +
>> +int qcom_icc_query_cmd(struct icc_path *path, u32 *cmd, u64 avg, u64 max)
>> +{
>> +	struct qcom_icc_node *qn;
>> +	int i, j, k = 0;
>> +
>> +	for (i = 0; i < path->num_nodes; i++) {
>> +		qn = path->reqs[i].node->data;
>> +		for (j = 0; j < qn->num_bcms; j++, k++)
>> +			cmd[k] = bcm_query(qn->bcms[j], avg, max);
>> +	}
>> +
>> +	return 0;
>> +}
> 
> Same as above.  When downstream did this for their old bespoke bus API they had
> one function returns a struct with addrs / commands / wait bitmask.
> 
> I don't mind splitting up the function, but either way something is going to
> have to query the number of commands in the path and allocate the buffers.
> 
> Jordan
> 
>> +EXPORT_SYMBOL_GPL(qcom_icc_query_cmd);
>> +
>>   /**
>>    * qcom_icc_bcm_init - populates bcm aux data and connect qnodes
>>    * @bcm: bcm to be initialized
>> diff --git a/include/soc/qcom/icc.h b/include/soc/qcom/icc.h
>> new file mode 100644
>> index 000000000000..8d0ddde49739
>> --- /dev/null
>> +++ b/include/soc/qcom/icc.h
>> @@ -0,0 +1,11 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +
>> +#ifndef __SOC_QCOM_ICC_H__
>> +#define __SOC_QCOM_ICC_H__
>> +
>> +#include <linux/interconnect.h>
>> +
>> +int qcom_icc_query_addr(struct icc_path *path, u32 *addr);
>> +int qcom_icc_query_cmd(struct icc_path *path, u32 *cmd, u64 avg, u64 max);
>> +
>> +#endif /* __SOC_QCOM_ICC_H__ */
>> -- 
>> 2.26.1
>>
> 

  reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01  4:25 Jonathan Marek
2020-07-01 16:56 ` Jordan Crouse
2020-07-01 17:03   ` Jonathan Marek [this message]
2020-07-13 15:24 ` Georgi Djakov
2020-07-13 15:33   ` Jonathan Marek
2020-07-13 17:22   ` Jordan Crouse

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