From: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
To: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
agross@kernel.org, bjorn.andersson@linaro.org,
lgirdwood@gmail.com, broonie@kernel.org, robh+dt@kernel.org,
plai@codeaurora.org, bgoswami@codeaurora.org, perex@perex.cz,
tiwai@suse.com, rohitkr@codeaurora.org,
linux-arm-msm@vger.kernel.org, alsa-devel@alsa-project.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
swboyd@chromium.org, judyhsiao@chromium.org
Subject: Re: [PATCH v2] ASoC: qcom: Fix for DMA interrupt clear reg overwriting
Date: Mon, 7 Jun 2021 20:34:06 +0530 [thread overview]
Message-ID: <8028139e-fe25-bb9e-3038-5180bc5f8ca3@codeaurora.org> (raw)
In-Reply-To: <ac3e70da-7d82-2021-3a25-08179aeb6b54@linaro.org>
Hi Srini,
Thanks for your review comments!!!
On 6/7/2021 8:20 PM, Srinivas Kandagatla wrote:
>
>
> On 05/06/2021 12:38, Srinivasa Rao Mandadapu wrote:
>> The DMA interrupt clear register overwritten during
>> simultaneous playback and capture in lpass platform
>> interrupt handler. It's causing playback or capture stuck
>> in similtaneous plaback on speaker and capture on dmic test.
>> Update appropriate reg fields of corresponding channel instead
>> of entire register write.
>>
>> Fixes: commit c5c8635a04711 ("ASoC: qcom: Add LPASS platform driver")
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
>> ---
>> sound/soc/qcom/lpass-platform.c | 17 +++++++++++------
>> 1 file changed, 11 insertions(+), 6 deletions(-)
>>
>> diff --git a/sound/soc/qcom/lpass-platform.c
>> b/sound/soc/qcom/lpass-platform.c
>> index 0df9481ea4c6..f220a2739ac3 100644
>> --- a/sound/soc/qcom/lpass-platform.c
>> +++ b/sound/soc/qcom/lpass-platform.c
>> @@ -526,7 +526,7 @@ static int lpass_platform_pcmops_trigger(struct
>> snd_soc_component *component,
>> return -EINVAL;
>> }
>> - ret = regmap_write(map, reg_irqclr, val_irqclr);
>> + ret = regmap_update_bits(map, reg_irqclr, val_irqclr,
>> val_irqclr);
>> if (ret) {
>> dev_err(soc_runtime->dev, "error writing to irqclear
>> reg: %d\n", ret);
>> return ret;
>> @@ -650,7 +650,7 @@ static irqreturn_t lpass_dma_interrupt_handler(
>> struct lpass_variant *v = drvdata->variant;
>> irqreturn_t ret = IRQ_NONE;
>> int rv;
>> - unsigned int reg = 0, val = 0;
>> + unsigned int reg, val, val_clr, val_mask;
>
> minor nit here, variable name val_clr is pretty confusing to readers,
> It might be okay for irq clr register but we are using the same name
> of writing to other registers. So can I suggest you to reuse val
> variable.
>
> other thing is val_mask, please rename this to mask and just set it in
> the start of function so you can avoid 3 extra lines below.
Ok will do accordingly and repost patch.
>
> Other than that patch looks good to me!
>
> --srini
>> struct regmap *map;
>> unsigned int dai_id = cpu_dai->driver->id;
>> @@ -676,8 +676,9 @@ static irqreturn_t lpass_dma_interrupt_handler(
>> return -EINVAL;
>> }
>> if (interrupts & LPAIF_IRQ_PER(chan)) {
>> -
>> - rv = regmap_write(map, reg, LPAIF_IRQ_PER(chan) | val);
>> + val_clr = LPAIF_IRQ_PER(chan) | val;
>> + val_mask = LPAIF_IRQ_ALL(chan);
>> + rv = regmap_update_bits(map, reg, val_mask, val_clr);
>> if (rv) {
>> dev_err(soc_runtime->dev,
>> "error writing to irqclear reg: %d\n", rv);
>> @@ -688,7 +689,9 @@ static irqreturn_t lpass_dma_interrupt_handler(
>> }
>> if (interrupts & LPAIF_IRQ_XRUN(chan)) {
>> - rv = regmap_write(map, reg, LPAIF_IRQ_XRUN(chan) | val);
>> + val_clr = (LPAIF_IRQ_XRUN(chan) | val);
>> + val_mask = LPAIF_IRQ_ALL(chan);
>> + rv = regmap_update_bits(map, reg, val_mask, val_clr);
>> if (rv) {
>> dev_err(soc_runtime->dev,
>> "error writing to irqclear reg: %d\n", rv);
>> @@ -700,7 +703,9 @@ static irqreturn_t lpass_dma_interrupt_handler(
>> }
>> if (interrupts & LPAIF_IRQ_ERR(chan)) {
>> - rv = regmap_write(map, reg, LPAIF_IRQ_ERR(chan) | val);
>> + val_clr = (LPAIF_IRQ_ERR(chan) | val);
>> + val_mask = LPAIF_IRQ_ALL(chan);
>> + rv = regmap_update_bits(map, reg, val_mask, val_clr);
>> if (rv) {
>> dev_err(soc_runtime->dev,
>> "error writing to irqclear reg: %d\n", rv);
>>
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc.,
is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
prev parent reply other threads:[~2021-06-07 15:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-05 11:38 [PATCH v2] ASoC: qcom: Fix for DMA interrupt clear reg overwriting Srinivasa Rao Mandadapu
2021-06-07 14:50 ` Srinivas Kandagatla
2021-06-07 15:04 ` Srinivasa Rao Mandadapu [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=8028139e-fe25-bb9e-3038-5180bc5f8ca3@codeaurora.org \
--to=srivasam@codeaurora.org \
--cc=agross@kernel.org \
--cc=alsa-devel@alsa-project.org \
--cc=bgoswami@codeaurora.org \
--cc=bjorn.andersson@linaro.org \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=judyhsiao@chromium.org \
--cc=lgirdwood@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=perex@perex.cz \
--cc=plai@codeaurora.org \
--cc=robh+dt@kernel.org \
--cc=rohitkr@codeaurora.org \
--cc=srinivas.kandagatla@linaro.org \
--cc=swboyd@chromium.org \
--cc=tiwai@suse.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).