From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Shawn Guo <shawn.guo@linaro.org>, Georgi Djakov <djakov@kernel.org>
Cc: AngeloGioacchino Del Regno <kholk11@gmail.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH] interconnect: qcom: sdm660: Correct NOC_QOS_PRIORITY shift and mask
Date: Wed, 1 Sep 2021 17:31:25 +0300 [thread overview]
Message-ID: <813898c9-5ad6-a98b-35a6-58f24a7cada2@linaro.org> (raw)
In-Reply-To: <20210823075405.382-1-shawn.guo@linaro.org>
On 23/08/2021 10:54, Shawn Guo wrote:
> The NOC_QOS_PRIORITY shift and mask do not match what vendor kernel
> defines [1]. Correct them per vendor kernel.
>
> [1] https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/soc/qcom/msm_bus/msm_bus_noc_adhoc.c?h=LA.UM.8.2.r1-04800-sdm660.0#n37
>
> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/interconnect/qcom/sdm660.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c
> index ac13046537e8..c89c991a80a0 100644
> --- a/drivers/interconnect/qcom/sdm660.c
> +++ b/drivers/interconnect/qcom/sdm660.c
> @@ -44,9 +44,10 @@
> #define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS)
>
> #define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
> -#define NOC_QOS_PRIORITY_MASK 0xf
> +#define NOC_QOS_PRIORITY_P1_MASK 0xc
> +#define NOC_QOS_PRIORITY_P0_MASK 0x3
> #define NOC_QOS_PRIORITY_P1_SHIFT 0x2
> -#define NOC_QOS_PRIORITY_P0_SHIFT 0x3
> +#define NOC_QOS_PRIORITY_P0_SHIFT 0x0
>
> #define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
> #define NOC_QOS_MODEn_MASK 0x3
> @@ -624,13 +625,13 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
> /* Must be updated one at a time, P1 first, P0 last */
> val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
> rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
> - NOC_QOS_PRIORITY_MASK, val);
> + NOC_QOS_PRIORITY_P1_MASK, val);
> if (rc)
> return rc;
>
> val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT;
> return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
> - NOC_QOS_PRIORITY_MASK, val);
> + NOC_QOS_PRIORITY_P0_MASK, val);
> }
>
> static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2021-09-01 14:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 7:54 [PATCH] interconnect: qcom: sdm660: Correct NOC_QOS_PRIORITY shift and mask Shawn Guo
2021-09-01 14:31 ` Dmitry Baryshkov [this message]
2021-09-01 14:51 ` AngeloGioacchino Del Regno
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