From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7156C4320A for ; Wed, 25 Aug 2021 14:23:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BD675610CF for ; Wed, 25 Aug 2021 14:23:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241494AbhHYOYj (ORCPT ); Wed, 25 Aug 2021 10:24:39 -0400 Received: from guitar.tcltek.co.il ([192.115.133.116]:43884 "EHLO mx.tkos.co.il" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241546AbhHYOY2 (ORCPT ); Wed, 25 Aug 2021 10:24:28 -0400 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id CE408440E88; Wed, 25 Aug 2021 17:23:29 +0300 (IDT) References: <87o89lahqp.fsf@tarshish> User-agent: mu4e 1.6.3; emacs 27.1 From: Baruch Siach To: Rob Herring Cc: Andy Gross , Bjorn Andersson , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Kishon Vijay Abraham I , Vinod Koul , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , devicetree@vger.kernel.org, linux-phy@lists.infradead.org, PCI , linux-arm-msm , linux-arm-kernel , linux-tegra Subject: Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller Date: Wed, 25 Aug 2021 17:09:49 +0300 In-reply-to: Message-ID: <87lf4pa9i0.fsf@tarshish> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Rob, On Wed, Aug 25 2021, Rob Herring wrote: > On Wed, Aug 25, 2021 at 6:25 AM Baruch Siach wrote: >> On Fri, Aug 06 2021, Rob Herring wrote: >> > On Wed, May 5, 2021 at 3:18 AM Baruch Siach wrote: >> >> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + >> >> + PCI_EXP_DEVCTL2); >> >> + >> >> + writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3, >> >> + pci->dbi_base + offset + PCI_EXP_DEVCTL2); >> > >> > Doesn't this overwrite the prior register write? >> >> It does. There are two mistakes here. The writel() above should set >> PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98). > > No. Did you check what 'offset' is? PCIE20_DEVICE_CONTROL2_STATUS2 is > PCI_EXP_DEVCTL2 plus the status reg. What's wrong is it should be a > 16-bit write. Thanks for enlightening me. 'offset' is 0x70 here. So PCI_EXP_DEVCTL2 is at 0x98, and PCI_EXP_LNKCTL2 is at 0xa0. Only the second writel() is wrong. But since generic code handles speed, I can drop it entirely. I see that dw_pcie_link_set_max_speed() uses dw_pcie_writel_dbi() to write to PCI_EXP_LNKCTL2. Is that 16-bit write? Why are pci_regs.h register offsets in decimal? >> This writel() should set >> PCIE20_LNK_CONTROL2_LINK_STATUS2 (offset 0xa0). So both are wrong. Thanks, baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -