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([2a01:e34:ed2f:f020:5ebd:8bd9:d549:4211]) by smtp.googlemail.com with ESMTPSA id e15sm3183114wrm.60.2021.06.21.04.17.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Jun 2021 04:17:33 -0700 (PDT) Subject: Re: [RESEND PATCH v2 2/2] cpuidle: qcom: Add SPM register data for MSM8226 To: Bartosz Dudziak , Rob Herring , Andy Gross , Bjorn Andersson , "Rafael J. Wysocki" , David Sterba , Jens Axboe , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Cc: Stephan Gerhold References: <20210612205335.9730-1-bartosz.dudziak@snejp.pl> <20210612205335.9730-3-bartosz.dudziak@snejp.pl> From: Daniel Lezcano Message-ID: <8d23a3b3-61ad-fabb-fa95-e0bebac2e0ee@linaro.org> Date: Mon, 21 Jun 2021 13:17:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210612205335.9730-3-bartosz.dudziak@snejp.pl> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 12/06/2021 22:53, Bartosz Dudziak wrote: > Add MSM8226 register data to SPM AVS Wrapper 2 (SAW2) power controller > driver. > > Reviewed-by: Stephan Gerhold > Signed-off-by: Bartosz Dudziak Bjorn ? Andy ? > --- > drivers/cpuidle/cpuidle-qcom-spm.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c > index adf91a6e4d..c0e7971da2 100644 > --- a/drivers/cpuidle/cpuidle-qcom-spm.c > +++ b/drivers/cpuidle/cpuidle-qcom-spm.c > @@ -87,6 +87,18 @@ static const struct spm_reg_data spm_reg_8974_8084_cpu = { > .start_index[PM_SLEEP_MODE_SPC] = 3, > }; > > +/* SPM register data for 8226 */ > +static const struct spm_reg_data spm_reg_8226_cpu = { > + .reg_offset = spm_reg_offset_v2_1, > + .spm_cfg = 0x0, > + .spm_dly = 0x3C102800, > + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, > + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, > + 0x80, 0x10, 0x26, 0x30, 0x0F }, > + .start_index[PM_SLEEP_MODE_STBY] = 0, > + .start_index[PM_SLEEP_MODE_SPC] = 5, > +}; > + > static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { > [SPM_REG_CFG] = 0x08, > [SPM_REG_SPM_CTL] = 0x20, > @@ -259,6 +271,8 @@ static struct spm_driver_data *spm_get_drv(struct platform_device *pdev, > } > > static const struct of_device_id spm_match_table[] = { > + { .compatible = "qcom,msm8226-saw2-v2.1-cpu", > + .data = &spm_reg_8226_cpu }, > { .compatible = "qcom,msm8974-saw2-v2.1-cpu", > .data = &spm_reg_8974_8084_cpu }, > { .compatible = "qcom,apq8084-saw2-v2.1-cpu", > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog