linux-arm-msm.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Rajendra Nayak <rnayak@codeaurora.org>
To: Matthias Kaehlcke <mka@chromium.org>
Cc: viresh.kumar@linaro.org, sboyd@kernel.org,
	bjorn.andersson@linaro.org, agross@kernel.org,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
	Sean Paul <sean@poorly.run>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v3 05/17] drm/msm/dpu: Use OPP API to set clk/perf state
Date: Wed, 29 Apr 2020 19:46:27 +0530	[thread overview]
Message-ID: <92892448-c10c-4440-4933-17706d46ef93@codeaurora.org> (raw)
In-Reply-To: <20200429001425.GL4525@google.com>


On 4/29/2020 5:44 AM, Matthias Kaehlcke wrote:
> On Tue, Apr 28, 2020 at 07:02:53PM +0530, Rajendra Nayak wrote:
>> On some qualcomm platforms DPU needs to express a perforamnce state
>> requirement on a power domain depennding on the clock rates.
>> Use OPP table from DT to register with OPP framework and use
>> dev_pm_opp_set_rate() to set the clk/perf state.
>>
>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>> Cc: Rob Clark <robdclark@gmail.com>
>> Cc: Sean Paul <sean@poorly.run>
>> Cc: dri-devel@lists.freedesktop.org
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c |  3 ++-
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       | 25 ++++++++++++++++++++++++-
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h       |  4 ++++
>>   3 files changed, 30 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>> index 11f2beb..fe5717df 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
>> @@ -7,6 +7,7 @@
>>   #include <linux/debugfs.h>
>>   #include <linux/errno.h>
>>   #include <linux/mutex.h>
>> +#include <linux/pm_opp.h>
>>   #include <linux/sort.h>
>>   #include <linux/clk.h>
>>   #include <linux/bitmap.h>
>> @@ -239,7 +240,7 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
>>   		rate = core_clk->max_rate;
>>   
>>   	core_clk->rate = rate;
>> -	return msm_dss_clk_set_rate(core_clk, 1);
>> +	return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
>>   }
>>   
>>   static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index ce19f1d..2f53bbf 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -10,6 +10,7 @@
>>   #include <linux/debugfs.h>
>>   #include <linux/dma-buf.h>
>>   #include <linux/of_irq.h>
>> +#include <linux/pm_opp.h>
>>   
>>   #include <drm/drm_crtc.h>
>>   #include <drm/drm_file.h>
>> @@ -1033,11 +1034,23 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
>>   	if (!dpu_kms)
>>   		return -ENOMEM;
>>   
>> +	dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
>> +	if (IS_ERR(dpu_kms->opp_table))
>> +		return PTR_ERR(dpu_kms->opp_table);
>> +	/* OPP table is optional */
>> +	ret = dev_pm_opp_of_add_table(dev);
>> +	if (!ret) {
>> +		dpu_kms->has_opp_table = true;
>> +	} else if (ret != -ENODEV) {
>> +		dev_err(dev, "Invalid OPP table in Device tree\n");
> 
> nit: s/Device/device/ ?
> 
> uber-nit: s/Invalid/invalid/
> 
>    most log messages in this file start with a lower case letter, except
>    for acronyms/register names
> 
> please also change it in the other drivers unless you disagree.

Sure, will do. Thanks.

> 
>> +		return ret;
>> +	}
>> +
>>   	mp = &dpu_kms->mp;
>>   	ret = msm_dss_parse_clock(pdev, mp);
>>   	if (ret) {
>>   		DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
>> -		return ret;
>> +		goto err;
>>   	}
>>   
>>   	platform_set_drvdata(pdev, dpu_kms);
>> @@ -1051,6 +1064,11 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
>>   
>>   	priv->kms = &dpu_kms->base;
>>   	return ret;
>> +err:
>> +	if (dpu_kms->has_opp_table)
>> +		dev_pm_opp_of_remove_table(dev);
>> +	dev_pm_opp_put_clkname(dpu_kms->opp_table);
>> +	return ret;
>>   }
>>   
>>   static void dpu_unbind(struct device *dev, struct device *master, void *data)
>> @@ -1059,6 +1077,9 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
>>   	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
>>   	struct dss_module_power *mp = &dpu_kms->mp;
>>   
>> +	if (dpu_kms->has_opp_table)
>> +		dev_pm_opp_of_remove_table(dev);
>> +	dev_pm_opp_put_clkname(dpu_kms->opp_table);
>>   	msm_dss_put_clk(mp->clk_config, mp->num_clk);
>>   	devm_kfree(&pdev->dev, mp->clk_config);
>>   	mp->num_clk = 0;
>> @@ -1090,6 +1111,8 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
>>   	struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
>>   	struct dss_module_power *mp = &dpu_kms->mp;
>>   
>> +	/* Drop the performance state vote */
>> +	dev_pm_opp_set_rate(dev, 0);
>>   	rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
>>   	if (rc)
>>   		DPU_ERROR("clock disable failed rc:%d\n", rc);
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> index 211f5de9..2a52e4e 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
>> @@ -128,6 +128,10 @@ struct dpu_kms {
>>   
>>   	struct platform_device *pdev;
>>   	bool rpm_enabled;
>> +
>> +	struct opp_table *opp_table;
>> +	bool has_opp_table;
>> +
>>   	struct dss_module_power mp;
>>   
>>   	/* reference count bandwidth requests, so we know when we can
> 
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

  reply	other threads:[~2020-04-29 14:16 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-28 13:32 [PATCH v3 00/17] DVFS for IO devices on sdm845 and sc7180 Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 01/17] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-28 22:49   ` Matthias Kaehlcke
2020-04-28 13:32 ` [PATCH v3 02/17] spi: spi-geni-qcom: " Rajendra Nayak
2020-04-28 23:04   ` Matthias Kaehlcke
2020-04-28 13:32 ` [PATCH v3 03/17] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2020-04-29  0:02   ` Matthias Kaehlcke
2020-04-29 14:15     ` Rajendra Nayak
2020-04-29 14:53       ` Rajendra Nayak
2020-04-29 16:10         ` Matthias Kaehlcke
2020-04-29 16:38           ` Rajendra Nayak
2020-04-30  6:15     ` Viresh Kumar
2020-04-28 13:32 ` [PATCH v3 04/17] arm64: dts: sc7180: " Rajendra Nayak
2020-06-25 15:17   ` Matthias Kaehlcke
2020-06-29 11:24     ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 05/17] drm/msm/dpu: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-28 16:32   ` Rob Clark
2020-04-29 14:07     ` Rajendra Nayak
2020-04-29  0:14   ` Matthias Kaehlcke
2020-04-29 14:16     ` Rajendra Nayak [this message]
2020-04-28 13:32 ` [PATCH v3 06/17] drm/msm: dsi: " Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 07/17] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2020-04-29  0:27   ` Matthias Kaehlcke
2020-04-29 14:18     ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 08/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 09/17] mmc: sdhci-msm: Fix error handling for dev_pm_opp_of_add_table() Rajendra Nayak
2020-04-28 18:29   ` Ulf Hansson
2020-04-29 14:09     ` Rajendra Nayak
2020-05-05 11:33       ` Ulf Hansson
2020-05-05 13:32         ` Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 10/17] arm64: dts: sdm845: Add sdhc opps and power-domains Rajendra Nayak
2020-04-28 13:32 ` [PATCH v3 11/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 12/17] media: venus: core: Add support for opp tables/perf voting Rajendra Nayak
2020-04-29  0:39   ` Matthias Kaehlcke
2020-04-29 14:19     ` Rajendra Nayak
2020-04-29 14:36   ` Stanimir Varbanov
2020-04-29 15:10     ` Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 13/17] arm64: dts: sdm845: Add OPP tables and power-domains for venus Rajendra Nayak
2020-04-29  0:42   ` Matthias Kaehlcke
2020-04-28 13:33 ` [PATCH v3 14/17] arm64: dts: sc7180: " Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-29  0:49   ` Matthias Kaehlcke
2020-04-29 14:21     ` Rajendra Nayak
2020-04-28 13:33 ` [PATCH v3 16/17] arm64: dts: sdm845: Add qspi opps and power-domains Rajendra Nayak
2020-04-29  0:52   ` Matthias Kaehlcke
2020-04-28 13:33 ` [PATCH v3 17/17] arm64: dts: sc7180: " Rajendra Nayak

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=92892448-c10c-4440-4933-17706d46ef93@codeaurora.org \
    --to=rnayak@codeaurora.org \
    --cc=agross@kernel.org \
    --cc=bjorn.andersson@linaro.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mka@chromium.org \
    --cc=robdclark@gmail.com \
    --cc=sboyd@kernel.org \
    --cc=sean@poorly.run \
    --cc=viresh.kumar@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).