From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F461C433EF for ; Tue, 7 Dec 2021 19:30:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229625AbhLGTeO (ORCPT ); Tue, 7 Dec 2021 14:34:14 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:51005 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229490AbhLGTeN (ORCPT ); Tue, 7 Dec 2021 14:34:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1638905443; x=1670441443; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=2+8+9+n+/aGNN1L02U2FSrNSkxhVLZ6+6C8+ofOOfN4=; b=FAKdPqX7NbmXyPc6Vl0W8Tu3s+ZU44G8WXTDR9Kh7991IkqoSnV0uUm1 7acliypz2Q1TLJ3HFY3sdXV601SJjRuIO3i/nWtoP0BSo7DMpX4ToeWa+ X4/MyQN1OYUJAcvmvQtn9DOnK/ag1H1uUOWH/g0Hs8WoYoXbRP4qezCc0 E=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 07 Dec 2021 11:30:43 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2021 11:30:42 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 7 Dec 2021 11:30:42 -0800 Received: from [10.111.164.126] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 7 Dec 2021 11:30:40 -0800 Message-ID: <9ca7a443-49ed-8eec-de0a-d95552988a0e@quicinc.com> Date: Tue, 7 Dec 2021 11:30:38 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH v2 1/4] drm/msm/dpu: drop scaler config from plane state Content-Language: en-US To: Dmitry Baryshkov , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar CC: Stephen Boyd , David Airlie , "Daniel Vetter" , , , References: <20211201225140.2481577-1-dmitry.baryshkov@linaro.org> <20211201225140.2481577-2-dmitry.baryshkov@linaro.org> From: Abhinav Kumar In-Reply-To: <20211201225140.2481577-2-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 12/1/2021 2:51 PM, Dmitry Baryshkov wrote: > Scaler and pixel_ext configuration does not contain a long living state, > it is used only during plane update, so remove these two fiels from > dpu_plane_state and allocate them on stack. s/fiels/fields apart from that, Reviewed-by: Abhinav Kumar > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 59 ++++++++++------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 6 --- > 2 files changed, 26 insertions(+), 39 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index ca190d92f0d5..4c373abbe89c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -536,14 +536,12 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, > struct dpu_plane_state *pstate, > uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, > struct dpu_hw_scaler3_cfg *scale_cfg, > + struct dpu_hw_pixel_ext *pixel_ext, > const struct dpu_format *fmt, > uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v) > { > uint32_t i; > > - memset(scale_cfg, 0, sizeof(*scale_cfg)); > - memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext)); > - > scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = > mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w); > scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = > @@ -582,9 +580,9 @@ static void _dpu_plane_setup_scaler3(struct dpu_plane *pdpu, > scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; > } > > - pstate->pixel_ext.num_ext_pxls_top[i] = > + pixel_ext->num_ext_pxls_top[i] = > scale_cfg->src_height[i]; > - pstate->pixel_ext.num_ext_pxls_left[i] = > + pixel_ext->num_ext_pxls_left[i] = > scale_cfg->src_width[i]; > } > if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) > @@ -662,6 +660,11 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, > struct dpu_hw_pipe_cfg *pipe_cfg) > { > const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); > + struct dpu_hw_scaler3_cfg scaler3_cfg; > + struct dpu_hw_pixel_ext pixel_ext; > + > + memset(&scaler3_cfg, 0, sizeof(scaler3_cfg)); > + memset(&pixel_ext, 0, sizeof(pixel_ext)); > > /* don't chroma subsample if decimating */ > /* update scaler. calculate default config for QSEED3 */ > @@ -670,8 +673,23 @@ static void _dpu_plane_setup_scaler(struct dpu_plane *pdpu, > drm_rect_height(&pipe_cfg->src_rect), > drm_rect_width(&pipe_cfg->dst_rect), > drm_rect_height(&pipe_cfg->dst_rect), > - &pstate->scaler3_cfg, fmt, > + &scaler3_cfg, &pixel_ext, fmt, > info->hsub, info->vsub); > + > + if (pdpu->pipe_hw->ops.setup_pe) > + pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > + &pixel_ext); > + > + /** > + * when programmed in multirect mode, scalar block will be > + * bypassed. Still we need to update alpha and bitwidth > + * ONLY for RECT0 > + */ > + if (pdpu->pipe_hw->ops.setup_scaler && > + pstate->multirect_index != DPU_SSPP_RECT_1) > + pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > + pipe_cfg, &pixel_ext, > + &scaler3_cfg); > } > > /** > @@ -712,7 +730,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, > drm_rect_width(&pipe_cfg.dst_rect); > pipe_cfg.src_rect.y2 = > drm_rect_height(&pipe_cfg.dst_rect); > - _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); > > if (pdpu->pipe_hw->ops.setup_format) > pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, > @@ -724,15 +741,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, > &pipe_cfg, > pstate->multirect_index); > > - if (pdpu->pipe_hw->ops.setup_pe) > - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > - &pstate->pixel_ext); > - > - if (pdpu->pipe_hw->ops.setup_scaler && > - pstate->multirect_index != DPU_SSPP_RECT_1) > - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > - &pipe_cfg, &pstate->pixel_ext, > - &pstate->scaler3_cfg); > + _dpu_plane_setup_scaler(pdpu, pstate, fmt, true, &pipe_cfg); > } > > return 0; > @@ -1129,8 +1138,6 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) > > pipe_cfg.dst_rect = state->dst; > > - _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); > - > /* override for color fill */ > if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { > /* skip remaining processing on color fill */ > @@ -1143,21 +1150,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) > pstate->multirect_index); > } > > - if (pdpu->pipe_hw->ops.setup_pe && > - (pstate->multirect_index != DPU_SSPP_RECT_1)) > - pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, > - &pstate->pixel_ext); > - > - /** > - * when programmed in multirect mode, scalar block will be > - * bypassed. Still we need to update alpha and bitwidth > - * ONLY for RECT0 > - */ > - if (pdpu->pipe_hw->ops.setup_scaler && > - pstate->multirect_index != DPU_SSPP_RECT_1) > - pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, > - &pipe_cfg, &pstate->pixel_ext, > - &pstate->scaler3_cfg); > + _dpu_plane_setup_scaler(pdpu, pstate, fmt, false, &pipe_cfg); > > if (pdpu->pipe_hw->ops.setup_multirect) > pdpu->pipe_hw->ops.setup_multirect( > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > index 52792526e904..1ee5ca5fcdf7 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h > @@ -23,8 +23,6 @@ > * @multirect_index: index of the rectangle of SSPP > * @multirect_mode: parallel or time multiplex multirect mode > * @pending: whether the current update is still pending > - * @scaler3_cfg: configuration data for scaler3 > - * @pixel_ext: configuration data for pixel extensions > * @plane_fetch_bw: calculated BW per plane > * @plane_clk: calculated clk per plane > */ > @@ -37,10 +35,6 @@ struct dpu_plane_state { > uint32_t multirect_mode; > bool pending; > > - /* scaler configuration */ > - struct dpu_hw_scaler3_cfg scaler3_cfg; > - struct dpu_hw_pixel_ext pixel_ext; > - > u64 plane_fetch_bw; > u64 plane_clk; > }; >