From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Benjamin Li <benl@squareup.com>
Cc: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
AngeloGioacchino Del Regno <kholk11@gmail.com>,
Harigovindan P <harigovi@codeaurora.org>,
Konrad Dybcio <konradybcio@gmail.com>,
zhengbin <zhengbin13@huawei.com>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@vger.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<dri-devel@lists.freedesktop.org>,
freedreno <freedreno@lists.freedesktop.org>,
open list <linux-kernel@vger.kernel.org>,
Anibal Limon <anibal.limon@linaro.org>
Subject: Re: [PATCH] drm/msm/dsi: save PLL registers across first PHY reset
Date: Sat, 30 Jan 2021 19:16:10 +0300 [thread overview]
Message-ID: <CAA8EJprOYwe8pSc+QzptVjxWKiTG-jGxoUh0aa5JTGq-4nnt+g@mail.gmail.com> (raw)
In-Reply-To: <eda75757-5cf2-14a7-3de4-ca57eb099cfd@squareup.com>
On Sat, 30 Jan 2021 at 05:00, Benjamin Li <benl@squareup.com> wrote:
>
>
> On 10/30/20 6:55 AM, Dmitry Baryshkov wrote:
> > Hello,
> >
> > On 07/10/2020 03:10, benl-kernelpatches@squareup.com wrote:
> >> From: Benjamin Li <benl@squareup.com>
> >>
> >> Take advantage of previously-added support for persisting PLL
> >> registers across DSI PHY disable/enable cycles (see 328e1a6
> >> 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
> >> support persisting across the very first DSI PHY enable at
> >> boot.
> >
> > Interesting enough, this breaks exactly on 8016. On DB410c with latest bootloader and w/o splash screen this patch causes boot freeze. Without this patch the board would successfully boot with display routed to HDMI.
>
> Hi Dimtry,
>
> Thanks for your fix for the DB410c breakage ("drm/msm/dsi: do not
> try reading 28nm vco rate if it's not enabled") that this patch
> causes.
>
> I re-tested my patch on top of qcom/linux for-next (3e6a8ce094759)
> which now has your fix, on a DB410c with HDMI display and no splash
> (which seems to be the default using the Linaro SD card image's LK),
> and indeed it is fixed.
>
> I assume you already also did the same & are okay with this going in.
> Appreciate the testing!
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested on RB5 and Dragonboard 845c (RB3).
--
With best wishes
Dmitry
next prev parent reply other threads:[~2021-01-30 16:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-07 0:10 [PATCH] drm/msm/dsi: save PLL registers across first PHY reset benl-kernelpatches
2020-10-30 13:55 ` Dmitry Baryshkov
2021-01-30 2:00 ` Benjamin Li
2021-01-30 16:16 ` Dmitry Baryshkov [this message]
2020-10-30 15:12 ` [PATCH] drm/msm/dsi: do not try reading 28nm vco rate if it's not enabled Dmitry Baryshkov
2020-12-29 20:15 ` patchwork-bot+linux-arm-msm
2021-05-15 0:33 ` [PATCH] drm/msm/dsi: save PLL registers across first PHY reset Dmitry Baryshkov
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