From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 405CBC433E6 for ; Sat, 30 Jan 2021 16:19:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1267F64E0F for ; Sat, 30 Jan 2021 16:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232236AbhA3QSp (ORCPT ); Sat, 30 Jan 2021 11:18:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230085AbhA3QRS (ORCPT ); Sat, 30 Jan 2021 11:17:18 -0500 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FE57C061573 for ; Sat, 30 Jan 2021 08:16:22 -0800 (PST) Received: by mail-qk1-x734.google.com with SMTP id r77so11877165qka.12 for ; Sat, 30 Jan 2021 08:16:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ejssOulrsTZ3ouHbrBBarxFuH2SuoMwxOAnWZQut8vY=; b=fmLNhBeiMEpCT64iXb708ra7uyU/Zu3j1K6JAv36RVHp01n5CleHqXKzoT74F9zaKL wncl6lJDD/PlSfUmmKmJdnMKUoo797O6FRVEjLRnyufjvFId6qRLeJQlRkiG6ypIC5+B fE5+v0pAHXXbvTEC65/I2ZAMahOFJe4XIbIutYTHZs4bANICZZw7g+HNQ5VwlgpOMUtv C1+rSGClaWl1qjmgmV0TJB9xn/iFlgNVbxQpxd+1m3AYeijxvhrI0sT6EDqPsgSEcUUO 72tMlzC4kQ4hJFXavIUisZ1M3dK7Yf0icFZeWv9toAeRTyfhzKK252rM9jUJSt6+cdA7 a77A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ejssOulrsTZ3ouHbrBBarxFuH2SuoMwxOAnWZQut8vY=; b=DafkmPhh2XBw3tjZCNBsTiNlGPw+tPAkNIJ3LbVYlU4t9oapzIvcTTyrTEQ7Ux2y2f H8HjlJJA2uG+phzfmJNM4Cwsrxm9dgepHch1AcJVfral5XRmXTVlzzhbiOI4zEdvbizx jJzPkjme7u6C4SbnhRePv5yKuF4FmIe6Vt2FaeW7jYG0h+bAuugzOc1xhkXOAh6HOWTM ZW/4sukbHJ4nv8tx/Gxndkt81A897nyFR4OERvGbd2oHI/MGMgHm290SFKTU/54ElI01 YPeIzag/FGwP4fPHGTpsH5XpkA5CkaDE2SQOT6qPW2K4ZYFC9wXQvHGuNEzVqx0Hr7Ir tWKA== X-Gm-Message-State: AOAM531v3lLhsra32Y+CwOQMYZbW2dFEWMCVRTXJvMWjb+2rBPAz72dF gKLk4NFzOuHpd4HlVvx4OCHCQDA77SK3BfuLjhaIKw== X-Google-Smtp-Source: ABdhPJxjFzuwpFzrLhh+nGrXrs4raiQtDHat0NUdPD5KVJSQnlTf0MuHS/yGpjPuaALH/of+u93L6laMiPrv5cVnAro= X-Received: by 2002:a05:620a:ec2:: with SMTP id x2mr8981436qkm.138.1612023381824; Sat, 30 Jan 2021 08:16:21 -0800 (PST) MIME-Version: 1.0 References: <010101750064e17e-3db0087e-fc37-494d-aac9-2c2b9b0a7c5b-000000@us-west-2.amazonses.com> <508ae9e2-5240-2f43-6c97-493bb7d9fbe8@linaro.org> In-Reply-To: From: Dmitry Baryshkov Date: Sat, 30 Jan 2021 19:16:10 +0300 Message-ID: Subject: Re: [PATCH] drm/msm/dsi: save PLL registers across first PHY reset To: Benjamin Li Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , AngeloGioacchino Del Regno , Harigovindan P , Konrad Dybcio , zhengbin , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno , open list , Anibal Limon Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sat, 30 Jan 2021 at 05:00, Benjamin Li wrote: > > > On 10/30/20 6:55 AM, Dmitry Baryshkov wrote: > > Hello, > > > > On 07/10/2020 03:10, benl-kernelpatches@squareup.com wrote: > >> From: Benjamin Li > >> > >> Take advantage of previously-added support for persisting PLL > >> registers across DSI PHY disable/enable cycles (see 328e1a6 > >> 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to > >> support persisting across the very first DSI PHY enable at > >> boot. > > > > Interesting enough, this breaks exactly on 8016. On DB410c with latest bootloader and w/o splash screen this patch causes boot freeze. Without this patch the board would successfully boot with display routed to HDMI. > > Hi Dimtry, > > Thanks for your fix for the DB410c breakage ("drm/msm/dsi: do not > try reading 28nm vco rate if it's not enabled") that this patch > causes. > > I re-tested my patch on top of qcom/linux for-next (3e6a8ce094759) > which now has your fix, on a DB410c with HDMI display and no splash > (which seems to be the default using the Linaro SD card image's LK), > and indeed it is fixed. > > I assume you already also did the same & are okay with this going in. > Appreciate the testing! Tested-by: Dmitry Baryshkov Tested on RB5 and Dragonboard 845c (RB3). -- With best wishes Dmitry