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[209.85.219.52]) by smtp.gmail.com with ESMTPSA id n92sm9412407qtd.68.2020.04.13.14.18.18 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Apr 2020 14:18:19 -0700 (PDT) Received: by mail-qv1-f52.google.com with SMTP id bu9so5147061qvb.13 for ; Mon, 13 Apr 2020 14:18:18 -0700 (PDT) X-Received: by 2002:a67:7141:: with SMTP id m62mr13509743vsc.73.1586812698026; Mon, 13 Apr 2020 14:18:18 -0700 (PDT) MIME-Version: 1.0 References: <20200413170415.32463-1-dianders@chromium.org> <20200413100321.v4.1.I1b754137e8089e46cf33fc2ea270734ec3847ec4@changeid> <6566837cdb0e8db522c53daba8baf49c2ca79376.camel@perches.com> In-Reply-To: <6566837cdb0e8db522c53daba8baf49c2ca79376.camel@perches.com> From: Doug Anderson Date: Mon, 13 Apr 2020 14:18:06 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 01/10] drivers: qcom: rpmh-rsc: Clean code reading/writing TCS regs/cmds To: Joe Perches Cc: Andy Gross , Bjorn Andersson , Maulik Shah , Stephen Boyd , Matthias Kaehlcke , Rajendra Nayak , Evan Green , Lina Iyer , linux-arm-msm , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Mon, Apr 13, 2020 at 11:21 AM Joe Perches wrote: > > On Mon, 2020-04-13 at 10:04 -0700, Douglas Anderson wrote: > > This patch makes two changes, both of which should be no-ops: > > > > 1. Make read_tcs_reg() / read_tcs_cmd() symmetric to write_tcs_reg() / > > write_tcs_cmd(). > > > > 2. Change the order of operations in the above functions to make it > > more obvious to me what the math is doing. Specifically first you > > want to find the right TCS, then the right register, and then > > multiply by the command ID if necessary. > > Though these operations are only used a couple times, perhaps > it'd be useful to have static inlines for the calcs. > > > diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c > [] > > @@ -67,28 +67,33 @@ > > #define CMD_STATUS_ISSUED BIT(8) > > #define CMD_STATUS_COMPL BIT(16) > > Maybe something like: > > static inline void __iomem * > tcs_reg_addr(struct rsc_drv drv, int reg, int tcs_id) > { > return drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg; > } > > static inline void __iomem * > tcs_cmd_addr(struct rsc_drv drv, int reg, int tcs_id, int cmd_id) > { > return tcs_reg_addr(drv, reg, tcs_id) + RSC_DRV_CMD_OFFSET * cmd_id; > } > > > -static u32 read_tcs_reg(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) > > +static u32 read_tcs_cmd(struct rsc_drv *drv, int reg, int tcs_id, int cmd_id) > > { > > - return readl_relaxed(drv->tcs_base + reg + RSC_DRV_TCS_OFFSET * tcs_id + > > + return readl_relaxed(drv->tcs_base + RSC_DRV_TCS_OFFSET * tcs_id + reg + > > RSC_DRV_CMD_OFFSET * cmd_id); > > return readl_relaxed(tcs_cmd_addr(drv, reg, tcs_id, cmd_id)); > > etc... I won't object if you really feel passionately about making that change but at this point it doesn't add tons of extra readability for me personally. I was kinda hoping that Maulik and my series could land in the next few days since having 16 patches outstanding gets a bit unwieldy. I'd rather not send out another spin of my series at this point since it's just a bunch more churn in everyone's inboxes. Maybe after they land you can post that as a follow-up cleanup? -Doug