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[209.85.222.45]) by smtp.gmail.com with ESMTPSA id j21sm795157vkn.26.2020.09.02.07.37.58 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2020 07:37:58 -0700 (PDT) Received: by mail-ua1-f45.google.com with SMTP id v24so1635772uaj.7 for ; Wed, 02 Sep 2020 07:37:58 -0700 (PDT) X-Received: by 2002:ab0:37d3:: with SMTP id e19mr5065664uav.64.1599057477726; Wed, 02 Sep 2020 07:37:57 -0700 (PDT) MIME-Version: 1.0 References: <20191218143416.v3.6.Iaf8d698f4e5253d658ae283d2fd07268076a7c27@changeid> <20200710011935.GA7056@gentoo.org> <8e306b6d-246d-aa7f-cb24-923e13afcd04@kali.org> In-Reply-To: From: Doug Anderson Date: Wed, 2 Sep 2020 07:37:46 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can To: Steev Klimaszewski Cc: Laurent Pinchart , Andrzej Hajda , David Airlie , Bjorn Andersson , Daniel Vetter , dri-devel , Jeffrey Hugo , Jernej Skrabec , Jonas Karlman , linux-arm-msm , LKML , Neil Armstrong , Rob Clark , Rob Clark , Sean Paul , Steev Klimaszewski Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Tue, Jul 14, 2020 at 8:31 AM Doug Anderson wrote: > > > Hopefully BOE gets back to you soon, and there's no rush, I'm just an > > end user who is extremely appreciative of all the work everyone on the > > list and the kernel in general put in to make my machines usable. > > Just FYI that I got confirmation that the panel is truly 6 bpp but it > will do FRC dithering if given an 8 bpp input. That means that you > should be getting just as good picture quality (and possibly more > tunable) by using the dithering in the display pipeline and leaving > the panel as 6bpp. Thus I'm going to assume that's the route we'll go > down. If ever we find someone that wants to use this panel on a > display controller that can't do its own dithering then I guess we'll > have to figure out what to do then... > > In terms of the more optimal pixel clock for saving power, my proposal > is still being analyzed and I'll report back when I hear more. I'm > seeing if BOE can confirm that my proposal will work both for my panel > (the -n62 variant) and the one you have (the -n61 variant). To close the loop here: we finally got back an official word that we shouldn't use my proposed timings that would have allowed us to move down to a 1.62 GHz pixel clock. Though they work most of the time, there are apparently some corner cases where they cause problems / flickering. :( While you could certainly use the timings on your own system if they happen to work for you, I don't think it'd be a good idea to switch the default over to them or anything. I'm told that hardware makers will take this type of thing into consideration for future hardware. -Doug