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[209.85.217.45]) by smtp.gmail.com with ESMTPSA id b18sm611140vsr.19.2020.10.16.20.18.08 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Oct 2020 20:18:08 -0700 (PDT) Received: by mail-vs1-f45.google.com with SMTP id l6so2554864vsr.7 for ; Fri, 16 Oct 2020 20:18:08 -0700 (PDT) X-Received: by 2002:a67:ec9a:: with SMTP id h26mr4216646vsp.34.1602904687735; Fri, 16 Oct 2020 20:18:07 -0700 (PDT) MIME-Version: 1.0 References: <20201014171259.v4.1.I4567b5e7e17bbb15ef063d447cb83fd43746cb18@changeid> <20201014171259.v4.3.Id0cc5d859e2422082a29a7909658932c857f5a81@changeid> <160281818774.884498.11509417433655580732@swboyd.mtv.corp.google.com> <160290009516.884498.11234055455838582432@swboyd.mtv.corp.google.com> In-Reply-To: <160290009516.884498.11234055455838582432@swboyd.mtv.corp.google.com> From: Doug Anderson Date: Fri, 16 Oct 2020 20:17:56 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/3] clk: qcom: lpasscc-sc7180: Re-configure the PLL in case lost To: Stephen Boyd Cc: Taniya Das , David Brown , "open list:ARM/QUALCOMM SUPPORT" , Rajendra Nayak , Andy Gross , Bjorn Andersson , Michael Turquette , linux-arm-msm , linux-clk , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Fri, Oct 16, 2020 at 7:01 PM Stephen Boyd wrote: > > Quoting Stephen Boyd (2020-10-15 20:16:27) > > Quoting Douglas Anderson (2020-10-14 17:13:29) > > > From: Taniya Das > > > > > > In the case where the PLL configuration is lost, then the pm runtime > > > resume will reconfigure before usage. > > > > Taniya, this commit needs a lot more describing than one sentence. I see > > that the PLL's L value is reset at boot, but only once. That seems to be > > because the bootloader I have doesn't set bit 11 for the RETAIN_FF bit > > on the lpass_core_hm_gdsc. Once the gdsc is turned off the first time, > > the PLL settings are lost and the L val is reset to 0. That makes sense > > because RETAIN_FF isn't set. This also means the other register writes > > during probe are lost during the first suspend of the lpass core clk > > controller. Then when the GDSC is turned on the next time for this clk > > controller being runtime resumed we will set the retain bit and then > > configure the PLL again. BTW, I see that runtime PM is called for this > > clk controller for all the clk operations. Maybe there should be some > > auto suspend timeout so that we're not toggling the gdsc constantly? > > > > I hacked up the GDSC code to set the bit at gdsc registration time and > > it seems to fix the problem I'm seeing (i.e. that the PLL is stuck, > > which should also be in the commit text here). When I try to set the bit > > in the bootloader though my kernel won't boot. I guess something is > > hanging the system if I enable the retain bit in the GDSC? > > > > After hacking on this for some time it looks like we can apply this > patch instead and things are good. The first two patches in this series > look mostly good to me minus some nitpicks so please resend. By this you mean the two newlines you mentioned on , right? I think all the rest of your comments were on patch #3 (this patch) which I think we're dropping. I'm happy to repost a v5 of just patches #1 and #2 with the newlines fixed next week, or I'm happy if you want to fix them when applying as you alluded to on the Chrome OS gerrit. Just let me know. I just want to make sure I'm not missing some other nits before I post the v5. ;-) -Doug