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[209.85.217.48]) by smtp.gmail.com with ESMTPSA id o36sm1522547uao.15.2020.01.30.13.19.18 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Jan 2020 13:19:18 -0800 (PST) Received: by mail-vs1-f48.google.com with SMTP id 7so3025255vsr.10 for ; Thu, 30 Jan 2020 13:19:18 -0800 (PST) X-Received: by 2002:a67:fa1a:: with SMTP id i26mr4644896vsq.169.1580419157458; Thu, 30 Jan 2020 13:19:17 -0800 (PST) MIME-Version: 1.0 References: <20200124224225.22547-1-dianders@chromium.org> <20200124144154.v2.5.If590c468722d2985cea63adf60c0d2b3098f37d9@changeid> <20200129005152.2A3ED205F4@mail.kernel.org> In-Reply-To: <20200129005152.2A3ED205F4@mail.kernel.org> From: Doug Anderson Date: Thu, 30 Jan 2020 13:19:05 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 05/10] clk: qcom: Fix sc7180 dispcc parent data To: Stephen Boyd Cc: Andy Gross , Bjorn Andersson , Rob Herring , Jeffrey Hugo , Taniya Das , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-arm-msm , Harigovindan P , Matthias Kaehlcke , kalyan_t@codeaurora.org, Mark Rutland , linux-clk , "Kristian H. Kristensen" , Michael Turquette , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Tue, Jan 28, 2020 at 4:51 PM Stephen Boyd wrote: > > Quoting Douglas Anderson (2020-01-24 14:42:20) > > > > diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c > > index 30c1e25d3edb..380eca3f847d 100644 > > --- a/drivers/clk/qcom/dispcc-sc7180.c > > +++ b/drivers/clk/qcom/dispcc-sc7180.c > > @@ -76,40 +76,32 @@ static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { > > > > static const struct parent_map disp_cc_parent_map_0[] = { > > { P_BI_TCXO, 0 }, > > - { P_CORE_BI_PLL_TEST_SE, 7 }, > > }; > > > > static const struct clk_parent_data disp_cc_parent_data_0[] = { > > - { .fw_name = "bi_tcxo" }, > > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > > + { .fw_name = "xo" }, > > If we can make the binding match the code here and keep saying "bi_tcxo" > then that is preferred. That way we don't have to see bi_tcxo changing > and qcom folks are happy to keep the weird name. The name in the binding > is really up to the binding writer. v3 is now out and it still says "bi_tcxo" and generally uses the "internal" name. The big exception is msm8998's gpucc. It seems like a whole bunch of work has been done to move that over to more "purist" (AKA logical) names and I didn't want to undo that work. If we should move msm8998 to match everyone else then hopefully someone can do it as a followup patch? > > }; > > > > static const struct parent_map disp_cc_parent_map_1[] = { > > { P_BI_TCXO, 0 }, > > { P_DP_PHY_PLL_LINK_CLK, 1 }, > > { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, > > - { P_CORE_BI_PLL_TEST_SE, 7 }, > > }; > [...] > > @@ -203,7 +188,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > > .clkr.hw.init = &(struct clk_init_data){ > > .name = "disp_cc_mdss_dp_aux_clk_src", > > .parent_data = disp_cc_parent_data_0, > > - .num_parents = 2, > > + .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > > Can you split this ARRAY_SIZE() stuff to another patch? That will keep > focus on what's relevant here without distracting from the patch > contents. I know that parent array size is changing, but I don't want it > to be changing this line too. It has been done. -Doug