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[209.85.217.41]) by smtp.gmail.com with ESMTPSA id c23sm1576748vsl.7.2020.04.02.13.15.45 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Apr 2020 13:15:45 -0700 (PDT) Received: by mail-vs1-f41.google.com with SMTP id x206so3429485vsx.5 for ; Thu, 02 Apr 2020 13:15:45 -0700 (PDT) X-Received: by 2002:a67:1e46:: with SMTP id e67mr3977870vse.106.1585858544905; Thu, 02 Apr 2020 13:15:44 -0700 (PDT) MIME-Version: 1.0 References: <20200311231348.129254-1-dianders@chromium.org> <20200311161104.RFT.v2.2.Iaddc29b72772e6ea381238a0ee85b82d3903e5f2@changeid> <1fd57a5e-067c-5b2e-c9d5-5a1836e55273@codeaurora.org> In-Reply-To: <1fd57a5e-067c-5b2e-c9d5-5a1836e55273@codeaurora.org> From: Doug Anderson Date: Thu, 2 Apr 2020 13:15:33 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFT PATCH v2 02/10] drivers: qcom: rpmh-rsc: Document the register layout better To: Maulik Shah Cc: Andy Gross , Bjorn Andersson , Matthias Kaehlcke , Rajendra Nayak , Evan Green , Lina Iyer , Stephen Boyd , linux-arm-msm , LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Wed, Apr 1, 2020 at 1:14 AM Maulik Shah wrote: > > > + * - The first TCS block is special in that it has registers to control > > + * interrupts (RSC_DRV_IRQ_XXX). Space for these registers is reserved > > + * in all TCS blocks to make the math easier, but only the first one > > + * matters. > > First TCS block is not special, the RSC_DRV_IRQ_XXX registers are common > for all Ah. I think I see it now. It's much easier to talk about this with my old struct definition. Right now I have it documented as: /* 0x2a0 = 672 bytes big (see RSC_DRV_TCS_OFFSET) */ struct tcs_hw { u32 irq_enable; u32 irq_status; u32 irq_clear; char opaque_00c[0x4]; u32 cmd_wait_for_cmpl; u32 control; u32 status; u32 cmd_enable; char opaque_020[0x10]; struct tcs_cmd_hw tcs_cmd_hw[MAX_CMDS_PER_TCS]; char opaque_170[0x130]; }; ...but you're saying that it's actually: /* 0x2a0 = 672 bytes big (see RSC_DRV_TCS_OFFSET) */ struct tcs_hw { u32 cmd_wait_for_cmpl; u32 control; u32 status; u32 cmd_enable; char opaque_010[0x10]; struct tcs_cmd_hw tcs_cmd_hw[MAX_CMDS_PER_TCS]; char opaque_160[0x140]; }; So it's still 672 bytes big but the extra "opaque" at the end is where those bytes go. Then, before the first TCS, there's actually 0x10 bytes of IRQ stuff. OK, I will adjust the diagrams. -Doug