Linux-ARM-MSM Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH] drm/msm/a6xx: Correct the highestbank configuration
@ 2020-01-24 12:20 Akhil P Oommen
  2020-01-24 15:46 ` [Freedreno] " Rob Clark
  2020-01-24 18:26 ` Jordan Crouse
  0 siblings, 2 replies; 5+ messages in thread
From: Akhil P Oommen @ 2020-01-24 12:20 UTC (permalink / raw)
  To: freedreno; +Cc: dri-devel, linux-arm-msm, linux-kernel, jcrouse, smasetty

Highest bank bit configuration is different for a618 gpu. Update
it with the correct configuration which is the reset value incidentally.

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index daf0780..536d196 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
 	/* Select CP0 to always count cycles */
 	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
 
-	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
-	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
-	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
-	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
+	if (adreno_is_a630(adreno_gpu)) {
+		gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
+		gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
+		gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
+		gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
+	}
 
 	/* Enable fault detection */
 	gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
-- 
2.7.4

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Freedreno] [PATCH] drm/msm/a6xx: Correct the highestbank configuration
  2020-01-24 12:20 [PATCH] drm/msm/a6xx: Correct the highestbank configuration Akhil P Oommen
@ 2020-01-24 15:46 ` " Rob Clark
  2020-01-24 18:26 ` Jordan Crouse
  1 sibling, 0 replies; 5+ messages in thread
From: Rob Clark @ 2020-01-24 15:46 UTC (permalink / raw)
  To: Akhil P Oommen
  Cc: freedreno, Sharat Masetty, linux-arm-msm, Jordan Crouse,
	dri-devel, Linux Kernel Mailing List

On Fri, Jan 24, 2020 at 5:50 AM Akhil P Oommen <akhilpo@codeaurora.org> wrote:
>
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
>
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>

Thanks, this fixes the UBWC issues on a618

Fixes: e812744c5f95 ("drm: msm: a6xx: Add support for A618")
Reviewed-by: Rob Clark <robdclark@gmail.com>

> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index daf0780..536d196 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
>         /* Select CP0 to always count cycles */
>         gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
>
> -       gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> -       gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> -       gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> -       gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> +       if (adreno_is_a630(adreno_gpu)) {
> +               gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> +               gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> +               gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> +               gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> +       }
>
>         /* Enable fault detection */
>         gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
> --
> 2.7.4
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] drm/msm/a6xx: Correct the highestbank configuration
  2020-01-24 12:20 [PATCH] drm/msm/a6xx: Correct the highestbank configuration Akhil P Oommen
  2020-01-24 15:46 ` [Freedreno] " Rob Clark
@ 2020-01-24 18:26 ` Jordan Crouse
  2020-01-31  7:59   ` Akhil P Oommen
  1 sibling, 1 reply; 5+ messages in thread
From: Jordan Crouse @ 2020-01-24 18:26 UTC (permalink / raw)
  To: Akhil P Oommen
  Cc: freedreno, dri-devel, linux-arm-msm, linux-kernel, smasetty

On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index daf0780..536d196 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
>  	/* Select CP0 to always count cycles */
>  	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
>  
> -	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> -	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> -	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> -	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> +	if (adreno_is_a630(adreno_gpu)) {
> +		gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> +		gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> +		gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> +		gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> +	}

it shouldn't come as a surprise that everything in the a6xx family is going to
have a highest bank bit setting. Even though the a618 uses the reset value, I
think it would be less confusing to future folks if we explicitly program it:

if (adreno_is_a630(adreno_dev))
  hbb = 2;
else
  hbb = 0;

....

Jordan

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH] drm/msm/a6xx: Correct the highestbank configuration
  2020-01-24 18:26 ` Jordan Crouse
@ 2020-01-31  7:59   ` Akhil P Oommen
  2020-02-11 15:38     ` [Freedreno] " Rob Clark
  0 siblings, 1 reply; 5+ messages in thread
From: Akhil P Oommen @ 2020-01-31  7:59 UTC (permalink / raw)
  To: freedreno, dri-devel, linux-arm-msm, linux-kernel, smasetty

On 1/24/2020 11:56 PM, Jordan Crouse wrote:
> On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
>> Highest bank bit configuration is different for a618 gpu. Update
>> it with the correct configuration which is the reset value incidentally.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
>> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
>>   1 file changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index daf0780..536d196 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
>>   	/* Select CP0 to always count cycles */
>>   	gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
>>   
>> -	gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
>> -	gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
>> -	gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
>> -	gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
>> +	if (adreno_is_a630(adreno_gpu)) {
>> +		gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
>> +		gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
>> +		gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
>> +		gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
>> +	}
> it shouldn't come as a surprise that everything in the a6xx family is going to
> have a highest bank bit setting. Even though the a618 uses the reset value, I
> think it would be less confusing to future folks if we explicitly program it:
>
> if (adreno_is_a630(adreno_dev))
>    hbb = 2;
> else
>    hbb = 0;

I think it would be better if we keep this in the adreno_info. Yes, this 
would waste a tiny bit of space for other gpu
entries in the gpulist. It is also possible to move this to a separate 
struct and keep a pointer to it in the adreno_info.
But that is something we should try when there are more a6xx specific 
configurations in future.

I have a new patch, but testing it is taking longer that I expected. I 
will share it as soon as possible.

> ....
>
> Jordan
>
Akhil

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [Freedreno] [PATCH] drm/msm/a6xx: Correct the highestbank configuration
  2020-01-31  7:59   ` Akhil P Oommen
@ 2020-02-11 15:38     ` " Rob Clark
  0 siblings, 0 replies; 5+ messages in thread
From: Rob Clark @ 2020-02-11 15:38 UTC (permalink / raw)
  To: Akhil P Oommen
  Cc: freedreno, dri-devel, linux-arm-msm, Linux Kernel Mailing List,
	Sharat Masetty

On Fri, Jan 31, 2020 at 12:00 AM Akhil P Oommen <akhilpo@codeaurora.org> wrote:
>
> On 1/24/2020 11:56 PM, Jordan Crouse wrote:
> > On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> >> Highest bank bit configuration is different for a618 gpu. Update
> >> it with the correct configuration which is the reset value incidentally.
> >>
> >> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> >> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
> >> ---
> >>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 ++++++----
> >>   1 file changed, 6 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> index daf0780..536d196 100644
> >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> >> @@ -470,10 +470,12 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
> >>      /* Select CP0 to always count cycles */
> >>      gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT);
> >>
> >> -    gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> >> -    gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> >> -    gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> >> -    gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> >> +    if (adreno_is_a630(adreno_gpu)) {
> >> +            gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1);
> >> +            gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1);
> >> +            gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1);
> >> +            gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21);
> >> +    }
> > it shouldn't come as a surprise that everything in the a6xx family is going to
> > have a highest bank bit setting. Even though the a618 uses the reset value, I
> > think it would be less confusing to future folks if we explicitly program it:
> >
> > if (adreno_is_a630(adreno_dev))
> >    hbb = 2;
> > else
> >    hbb = 0;
>
> I think it would be better if we keep this in the adreno_info. Yes, this
> would waste a tiny bit of space for other gpu
> entries in the gpulist. It is also possible to move this to a separate
> struct and keep a pointer to it in the adreno_info.
> But that is something we should try when there are more a6xx specific
> configurations in future.
>
> I have a new patch, but testing it is taking longer that I expected. I
> will share it as soon as possible.
>

I'm going to pull this in as-is for msm-fixes.  Please rebase the
change that you haven't posted yet on top of this patch, and send it
as a cleanup for the next cycle.  Thanks

BR,
-R

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, back to index

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-24 12:20 [PATCH] drm/msm/a6xx: Correct the highestbank configuration Akhil P Oommen
2020-01-24 15:46 ` [Freedreno] " Rob Clark
2020-01-24 18:26 ` Jordan Crouse
2020-01-31  7:59   ` Akhil P Oommen
2020-02-11 15:38     ` [Freedreno] " Rob Clark

Linux-ARM-MSM Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-msm/0 linux-arm-msm/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-msm linux-arm-msm/ https://lore.kernel.org/linux-arm-msm \
		linux-arm-msm@vger.kernel.org
	public-inbox-index linux-arm-msm

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.kernel.vger.linux-arm-msm


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git