From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B327C433E2 for ; Tue, 8 Sep 2020 16:58:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB8A5208FE for ; Tue, 8 Sep 2020 16:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599584301; bh=lq9eTjrWEGZEa2yiJKmSBpUchaqnuHBGfVpng6L9Aqc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=FCVaWGg/JIJd7Ir3SvEZGoPWR7WqHsmJS2xz7tvVg62VJVPRKsVHnDQTs3Sigwu7h rmP0/OrkXoqjzvKbCv1vzwTRUURDIiutCZoqHfzwtxAyTQ5rphLO9WkI7NQU7fKAO/ I8jZhBRkBPALMxySzLaoY/QKM9uz/iDu2Eg+m168= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731888AbgIHQ6U (ORCPT ); Tue, 8 Sep 2020 12:58:20 -0400 Received: from mail.kernel.org ([198.145.29.99]:58968 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731840AbgIHQUN (ORCPT ); Tue, 8 Sep 2020 12:20:13 -0400 Received: from mail-ua1-f42.google.com (mail-ua1-f42.google.com [209.85.222.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8B21C221EA for ; Tue, 8 Sep 2020 12:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1599567012; bh=lq9eTjrWEGZEa2yiJKmSBpUchaqnuHBGfVpng6L9Aqc=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=2JBREKU6JRgGxsJ1r8Ce2Iju6vIu8ns/qPUApwNkh+GlxhyVWmZki8K1pkhPaBIMI oIjpxoan1Owvg0lws/TNOUleSTdKu7+AxYmUfIWC1QVQyHVnrSntCmcm31oOP9BeIn XhujwMCmWKaMS2a2Z8abpw9lH+pT866FkY6uho3Y= Received: by mail-ua1-f42.google.com with SMTP id v5so4756787uau.10 for ; Tue, 08 Sep 2020 05:10:12 -0700 (PDT) X-Gm-Message-State: AOAM532zjKjhcSiqShfqTzUuykcgPYXEY/a/V02ES3eqinDx2cn5kxKU WIPj8TxgzkoNRziY0wkCfnXRyzby4i4x8JwcePSruA== X-Google-Smtp-Source: ABdhPJzVyQm6/6q5OjrV7nqU3MI7oMJGT7K1lFXypEJBdr8i/tOI9S8ZGFWCl5CSa7p27tf/aSMle29PYGnK5195eZQ= X-Received: by 2002:ab0:384a:: with SMTP id h10mr5065875uaw.77.1599567011727; Tue, 08 Sep 2020 05:10:11 -0700 (PDT) MIME-Version: 1.0 References: <20200908075716.30357-1-manivannan.sadhasivam@linaro.org> <20200908075716.30357-7-manivannan.sadhasivam@linaro.org> In-Reply-To: <20200908075716.30357-7-manivannan.sadhasivam@linaro.org> From: Amit Kucheria Date: Tue, 8 Sep 2020 17:40:00 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 6/7] cpufreq: qcom-hw: Add cpufreq support for SM8250 SoC To: Manivannan Sadhasivam Cc: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Andy Gross , Bjorn Andersson , Linux PM list , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , LKML , linux-arm-msm , Dmitry Baryshkov , Taniya Das Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue, Sep 8, 2020 at 1:27 PM Manivannan Sadhasivam wrote: > > SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add > support for it in the driver with relevant of_match data. > > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Amit Kucheria > --- > drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c > index de816bcafd33..c3c397cc3dc6 100644 > --- a/drivers/cpufreq/qcom-cpufreq-hw.c > +++ b/drivers/cpufreq/qcom-cpufreq-hw.c > @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = { > .lut_row_size = 32, > }; > > +static const struct qcom_cpufreq_soc_data sm8250_soc_data = { > + .reg_enable = 0x0, > + .reg_freq_lut = 0x100, > + .reg_volt_lut = 0x200, > + .reg_perf_state = 0x320, > + .lut_row_size = 4, > +}; > + > static const struct of_device_id qcom_cpufreq_hw_match[] = { > { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data }, > + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data }, > {} > }; > MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match); > -- > 2.17.1 >