From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36FF6C4320A for ; Wed, 25 Aug 2021 15:04:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1B594610FA for ; Wed, 25 Aug 2021 15:04:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239899AbhHYPEv (ORCPT ); Wed, 25 Aug 2021 11:04:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:56774 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231995AbhHYPEu (ORCPT ); Wed, 25 Aug 2021 11:04:50 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A202861176; Wed, 25 Aug 2021 15:04:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629903844; bh=SQu8ZriBWtkrMhexm27oLfTLE3woK/0rAxCFoPeJSWs=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=IkW0uZDXe3xbv33KgBw8Bo8H2mB81KwIUiIRJgNP9/vTaKWXH2sxZJrN4+oO1nMxQ YplMbJk33i1nTVfjIzni2O6dVbOMkObGGFB8oEI0wE7XVQh5r1HHJ3fzyzv43b48E/ s/1FBAQc2gRVVUILKtSOpR+AxQGCmSfQGqbQEK7NFCKk/cCWbKFIpsBozaZn81414n TeMharqkFIFQKYjkkMu62pMuUgOCwjxLCo4LgmfECxfA6LUVZ4THpARepXaPGu69tA Q2D/PyjaRO8x68LPnYZjWzI14snOQ+Z5kT2Vhrl2izpFPfCC5xTBHPj1SfSad++V6z //mmZeEZTboqg== Received: by mail-ej1-f54.google.com with SMTP id t19so2195260ejr.8; Wed, 25 Aug 2021 08:04:04 -0700 (PDT) X-Gm-Message-State: AOAM533wV9aUqc9RnGjHEAwSS4inPiKQ7udVtvieOX3gg8Ddgt7efDsF TNaC0qGAe21GvrwDDVS0Cx7hJG7aNrEUcgAxWw== X-Google-Smtp-Source: ABdhPJxewKcJ+3Eb7Es36Smt8z5TpesvKwiuyO4A/wqa6BX0T3ZI8RR8aZzlwJux6eaj2JM70CZMGA4Mxv1AsLONrLQ= X-Received: by 2002:a17:906:ff41:: with SMTP id zo1mr16030386ejb.525.1629903843136; Wed, 25 Aug 2021 08:04:03 -0700 (PDT) MIME-Version: 1.0 References: <87o89lahqp.fsf@tarshish> <87lf4pa9i0.fsf@tarshish> In-Reply-To: <87lf4pa9i0.fsf@tarshish> From: Rob Herring Date: Wed, 25 Aug 2021 10:03:51 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller To: Baruch Siach Cc: Andy Gross , Bjorn Andersson , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Kishon Vijay Abraham I , Vinod Koul , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , devicetree@vger.kernel.org, linux-phy@lists.infradead.org, PCI , linux-arm-msm , linux-arm-kernel , linux-tegra Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Aug 25, 2021 at 9:23 AM Baruch Siach wrote: > > Hi Rob, > > On Wed, Aug 25 2021, Rob Herring wrote: > > On Wed, Aug 25, 2021 at 6:25 AM Baruch Siach wrote: > >> On Fri, Aug 06 2021, Rob Herring wrote: > >> > On Wed, May 5, 2021 at 3:18 AM Baruch Siach wrote: > >> >> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + > >> >> + PCI_EXP_DEVCTL2); > >> >> + > >> >> + writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3, > >> >> + pci->dbi_base + offset + PCI_EXP_DEVCTL2); > >> > > >> > Doesn't this overwrite the prior register write? > >> > >> It does. There are two mistakes here. The writel() above should set > >> PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98). > > > > No. Did you check what 'offset' is? PCIE20_DEVICE_CONTROL2_STATUS2 is > > PCI_EXP_DEVCTL2 plus the status reg. What's wrong is it should be a > > 16-bit write. > > Thanks for enlightening me. 'offset' is 0x70 here. So PCI_EXP_DEVCTL2 is > at 0x98, and PCI_EXP_LNKCTL2 is at 0xa0. Only the second writel() is > wrong. But since generic code handles speed, I can drop it entirely. > > I see that dw_pcie_link_set_max_speed() uses dw_pcie_writel_dbi() to > write to PCI_EXP_LNKCTL2. Is that 16-bit write? No, that may be because some platforms can only do 32-bit accesses and dw_pcie_writew_dbi would be a RMW in that case. Or maybe there's some reliance on clearing the status register. > Why are pci_regs.h register offsets in decimal? No idea... Rob