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* [PATCHv3 0/2] coresight: etm4x: Add support to skip trace unit power up
@ 2020-05-15 16:22 Sai Prakash Ranjan
  2020-05-15 16:22 ` [PATCHv3 1/2] " Sai Prakash Ranjan
  2020-05-15 16:22 ` [PATCHv3 2/2] dt-bindings: arm: coresight: " Sai Prakash Ranjan
  0 siblings, 2 replies; 4+ messages in thread
From: Sai Prakash Ranjan @ 2020-05-15 16:22 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree, Rob Herring
  Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
	linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan

This series adds support to skip powering up of trace unit on systems
with an errata which stops CPU watchdog counter when power up bit is
set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm
Technologies Inc. chipsets where this errata exists since the ETMs
are in the same power domain as their respective CPU cores.

Changes since v2:
 * Fix checkpatch warning for 80 characters.

Changes since v1:
 * Use qcom,skip-power-up for naming as suggested by Mathieu.
 * Have check for DT property in initialization as per Mathieu.
 * Reword description for property as per Mathieu.
 * Split up dt-binding patch as checkpatch complains.

Tingwei Zhang (2):
  coresight: etm4x: Add support to skip trace unit power up
  dt-bindings: arm: coresight: Add support to skip trace unit power up

 .../devicetree/bindings/arm/coresight.txt     |  7 +++++
 drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
 drivers/hwtracing/coresight/coresight-etm4x.h |  3 +++
 3 files changed, 27 insertions(+), 10 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCHv3 1/2] coresight: etm4x: Add support to skip trace unit power up
  2020-05-15 16:22 [PATCHv3 0/2] coresight: etm4x: Add support to skip trace unit power up Sai Prakash Ranjan
@ 2020-05-15 16:22 ` Sai Prakash Ranjan
  2020-05-15 16:22 ` [PATCHv3 2/2] dt-bindings: arm: coresight: " Sai Prakash Ranjan
  1 sibling, 0 replies; 4+ messages in thread
From: Sai Prakash Ranjan @ 2020-05-15 16:22 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree, Rob Herring
  Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
	linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan

From: Tingwei Zhang <tingwei@codeaurora.org>

On some Qualcomm Technologies Inc. SoCs like SC7180, there
exists a hardware errata where the APSS (Application Processor
SubSystem)/CPU watchdog counter is stopped when the trace unit
power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs
share the same power domain as that of respective CPU cores,
they are powered on when the CPU core is powered on. So we can
skip powering up of trace unit after checking for this errata
via new property called "qcom,skip-power-up".

Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
 drivers/hwtracing/coresight/coresight-etm4x.h |  3 +++
 2 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index fb0f5f4f3a91..c16532e1e968 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -196,12 +196,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 	writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 
-	/*
-	 * Request to keep the trace unit powered and also
-	 * emulation of powerdown
-	 */
-	writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
-		       drvdata->base + TRCPDCR);
+	if (!drvdata->skip_power_up) {
+		/*
+		 * Request to keep the trace unit powered and also
+		 * emulation of powerdown
+		 */
+		writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) |
+			       TRCPDCR_PU, drvdata->base + TRCPDCR);
+	}
 
 	/* Enable the trace unit */
 	writel_relaxed(1, drvdata->base + TRCPRGCTLR);
@@ -476,10 +478,12 @@ static void etm4_disable_hw(void *info)
 
 	CS_UNLOCK(drvdata->base);
 
-	/* power can be removed from the trace unit now */
-	control = readl_relaxed(drvdata->base + TRCPDCR);
-	control &= ~TRCPDCR_PU;
-	writel_relaxed(control, drvdata->base + TRCPDCR);
+	if (!drvdata->skip_power_up) {
+		/* power can be removed from the trace unit now */
+		control = readl_relaxed(drvdata->base + TRCPDCR);
+		control &= ~TRCPDCR_PU;
+		writel_relaxed(control, drvdata->base + TRCPDCR);
+	}
 
 	control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 
@@ -1429,6 +1433,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 			return -ENOMEM;
 	}
 
+	if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
+		drvdata->skip_power_up = true;
+
 	/* Validity for the resource is already checked by the AMBA core */
 	base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(base))
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 4a695bf90582..72c9a55e67df 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -407,6 +407,8 @@ struct etmv4_save_state {
  * @config:	structure holding configuration parameters.
  * @save_state:	State to be preserved across power loss
  * @state_needs_restore: True when there is context to restore after PM exit
+ * @skip_power_up: Indicates if an implementation can skip powering up
+ *		   the trace unit.
  */
 struct etmv4_drvdata {
 	void __iomem			*base;
@@ -454,6 +456,7 @@ struct etmv4_drvdata {
 	struct etmv4_config		config;
 	struct etmv4_save_state		*save_state;
 	bool				state_needs_restore;
+	bool				skip_power_up;
 };
 
 /* Address comparator access types */
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
  2020-05-15 16:22 [PATCHv3 0/2] coresight: etm4x: Add support to skip trace unit power up Sai Prakash Ranjan
  2020-05-15 16:22 ` [PATCHv3 1/2] " Sai Prakash Ranjan
@ 2020-05-15 16:22 ` Sai Prakash Ranjan
  2020-05-21 15:53   ` Mathieu Poirier
  1 sibling, 1 reply; 4+ messages in thread
From: Sai Prakash Ranjan @ 2020-05-15 16:22 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree, Rob Herring
  Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
	linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan

From: Tingwei Zhang <tingwei@codeaurora.org>

Add "qcom,skip-power-up" property to identify systems which can
skip powering up of trace unit since they share the same power
domain as their CPU core. This is required to identify such
systems with hardware errata which stops the CPU watchdog counter
when the power up bit is set (TRCPDCR.PU).

Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 846f6daae71b..e4b2eda0b53b 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -108,6 +108,13 @@ its hardware characteristcs.
 	* arm,cp14: must be present if the system accesses ETM/PTM management
 	  registers via co-processor 14.
 
+	* qcom,skip-power-up: boolean. Indicates that an implementation can
+	  skip powering up the trace unit. TRCPDCR.PU does not have to be set
+	  on Qualcomm Technologies Inc. systems since ETMs are in the same power
+	  domain as their CPU cores. This property is required to identify such
+	  systems with hardware errata where the CPU watchdog counter is stopped
+	  when TRCPDCR.PU is set.
+
 * Optional property for TMC:
 
 	* arm,buffer-size: size of contiguous buffer space for TMC ETR
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
  2020-05-15 16:22 ` [PATCHv3 2/2] dt-bindings: arm: coresight: " Sai Prakash Ranjan
@ 2020-05-21 15:53   ` Mathieu Poirier
  0 siblings, 0 replies; 4+ messages in thread
From: Mathieu Poirier @ 2020-05-21 15:53 UTC (permalink / raw)
  To: Sai Prakash Ranjan
  Cc: Suzuki K Poulose, Mike Leach, devicetree, Rob Herring,
	Stephen Boyd, Leo Yan, linux-arm-kernel,
	Linux Kernel Mailing List, linux-arm-msm, Tingwei Zhang,
	Coresight ML

On Fri, 15 May 2020 at 10:23, Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> From: Tingwei Zhang <tingwei@codeaurora.org>
>
> Add "qcom,skip-power-up" property to identify systems which can
> skip powering up of trace unit since they share the same power
> domain as their CPU core. This is required to identify such
> systems with hardware errata which stops the CPU watchdog counter
> when the power up bit is set (TRCPDCR.PU).
>
> Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
> Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 846f6daae71b..e4b2eda0b53b 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -108,6 +108,13 @@ its hardware characteristcs.
>         * arm,cp14: must be present if the system accesses ETM/PTM management
>           registers via co-processor 14.
>
> +       * qcom,skip-power-up: boolean. Indicates that an implementation can
> +         skip powering up the trace unit. TRCPDCR.PU does not have to be set
> +         on Qualcomm Technologies Inc. systems since ETMs are in the same power
> +         domain as their CPU cores. This property is required to identify such
> +         systems with hardware errata where the CPU watchdog counter is stopped
> +         when TRCPDCR.PU is set.
> +
>  * Optional property for TMC:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

>
>         * arm,buffer-size: size of contiguous buffer space for TMC ETR
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 4+ messages in thread

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Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2020-05-15 16:22 [PATCHv3 0/2] coresight: etm4x: Add support to skip trace unit power up Sai Prakash Ranjan
2020-05-15 16:22 ` [PATCHv3 1/2] " Sai Prakash Ranjan
2020-05-15 16:22 ` [PATCHv3 2/2] dt-bindings: arm: coresight: " Sai Prakash Ranjan
2020-05-21 15:53   ` Mathieu Poirier

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