From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1B69C48BD3 for ; Wed, 26 Jun 2019 17:42:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 812CB21743 for ; Wed, 26 Jun 2019 17:42:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="onBGOizx" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726387AbfFZRmK (ORCPT ); Wed, 26 Jun 2019 13:42:10 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:46029 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726239AbfFZRmK (ORCPT ); Wed, 26 Jun 2019 13:42:10 -0400 Received: by mail-io1-f67.google.com with SMTP id e3so6839885ioc.12 for ; Wed, 26 Jun 2019 10:42:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ZKsEzAEn+zTozZeyiV/e1LwfvFOgAuBk1MCTImiKLZA=; b=onBGOizxsfiCRd7+gXbaT4hAW6mqsDds5B4NbecGa5qCbrZwUlZKaUd8d9sc91lChN 6p5GnD6ymeH10NabPIoVjBxJ2cieNgGYlB7B2r47VOuUCSzlgnGhfpMC12zEohslJRMy YGkCnl6tXZ+lCkt57UOzxqs04jbh4VNyBHxxAYH4lAI2Eg0ZKN2e5XExnBhMHhCqgrlm WjffAFmf1Yu2L9onBnMGPP8XZ1pzdMJebNqHY6nbp8CcAP04BXFe4GZpZiFbVTWdQdX8 J136o+dqdFHN6P0Ge8G2KnzX/2vsduc71V5PcFarONPkW4LBJ+ECv0Z+8zmthoeVj4Sx 2UFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ZKsEzAEn+zTozZeyiV/e1LwfvFOgAuBk1MCTImiKLZA=; b=SGUO6SICLHkax7QYxmhvMqVG9grnwjf1KNGwW5wUJuFehMxDJjGEtCg+NbzX+S9LTR h8WMgoCF3VhTJJz4xBVKo8UFVHV5AAmXMz1yqlsYBQJmL2sePnCKD4WKaoCl7AAnEF11 G49GW/aPYbKzFuUdDy49gstrJmBCa52Poieh95wO4T+dRfFr3d3G9qErsWBWY/hzjEts G4zlz7AApQwi0m2UI2bmG+APQG90nKpWxXoacIEHome6nptFv6Zo/7UBWMeqQbErtDGK Zk8PJcYOTTV6/i3isSeqBk6E2kDQ0wgZi8QZ/BYQRLe02g47QIGTB8WA9iE8wjvPMfUT TgfQ== X-Gm-Message-State: APjAAAUamKE0RRF+RDUnJY9XueN2LcdglaRqE7n+2HyWUDkgAUW8oiv8 msPD5VmpDG26DT3inKYb/Utlx0Qn1UZidOcpBvq5YQ== X-Google-Smtp-Source: APXvYqzP67fOblQX+UL3RTr8NEKsVBKZNmmryeKDByfNumC6w51Z6JbSESfRJHVRXeUS4Dcqs0atYnirT3xgPzBD4GQ= X-Received: by 2002:a5d:9613:: with SMTP id w19mr6438554iol.140.1561570929448; Wed, 26 Jun 2019 10:42:09 -0700 (PDT) MIME-Version: 1.0 References: <635466ab6a27781966bb083e93d2ca2729473ced.1561346998.git.saiprakash.ranjan@codeaurora.org> In-Reply-To: <635466ab6a27781966bb083e93d2ca2729473ced.1561346998.git.saiprakash.ranjan@codeaurora.org> From: Mathieu Poirier Date: Wed, 26 Jun 2019 11:41:58 -0600 Message-ID: Subject: Re: [PATCHv3 1/1] coresight: Do not default to CPU0 for missing CPU phandle To: Sai Prakash Ranjan Cc: Suzuki K Poulose , Leo Yan , Rob Herring , devicetree@vger.kernel.org, Alexander Shishkin , Andy Gross , David Brown , Mark Rutland , Rajendra Nayak , Vivek Gautam , Sibi Sankar , linux-arm-kernel , Linux Kernel Mailing List , linux-arm-msm Content-Type: text/plain; charset="UTF-8" Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Sai, On Sun, 23 Jun 2019 at 21:36, Sai Prakash Ranjan wrote: > > Coresight platform support assumes that a missing "cpu" phandle > defaults to CPU0. This could be problematic and unnecessarily binds > components to CPU0, where they may not be. Let us make the DT binding > rules a bit stricter by not defaulting to CPU0 for missing "cpu" > affinity information. > > Also in coresight etm and cpu-debug drivers, abort the probe > for such cases. > > Signed-off-by: Sai Prakash Ranjan > --- > .../bindings/arm/coresight-cpu-debug.txt | 4 ++-- > .../devicetree/bindings/arm/coresight.txt | 8 +++++--- > .../hwtracing/coresight/coresight-cpu-debug.c | 3 +++ > drivers/hwtracing/coresight/coresight-etm3x.c | 3 +++ > drivers/hwtracing/coresight/coresight-etm4x.c | 3 +++ > drivers/hwtracing/coresight/coresight-platform.c | 16 ++++++++-------- > 6 files changed, 24 insertions(+), 13 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > index 298291211ea4..f1de3247c1b7 100644 > --- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt > @@ -26,8 +26,8 @@ Required properties: > processor core is clocked by the internal CPU clock, so it > is enabled with CPU clock by default. > > -- cpu : the CPU phandle the debug module is affined to. When omitted > - the module is considered to belong to CPU0. > +- cpu : the CPU phandle the debug module is affined to. Do not assume it > + to default to CPU0 if omitted. > > Optional properties: > > diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt > index 8a88ddebc1a2..fcc3bacfd8bc 100644 > --- a/Documentation/devicetree/bindings/arm/coresight.txt > +++ b/Documentation/devicetree/bindings/arm/coresight.txt > @@ -59,6 +59,11 @@ its hardware characteristcs. > > * port or ports: see "Graph bindings for Coresight" below. > > +* Additional required property for Embedded Trace Macrocell (version 3.x and > + version 4.x): > + * cpu: the cpu phandle this ETM/PTM is affined to. Do not > + assume it to default to CPU0 if omitted. > + > * Additional required properties for System Trace Macrocells (STM): > * reg: along with the physical base address and length of the register > set as described above, another entry is required to describe the > @@ -87,9 +92,6 @@ its hardware characteristcs. > * arm,cp14: must be present if the system accesses ETM/PTM management > registers via co-processor 14. > > - * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the > - source is considered to belong to CPU0. > - > * Optional property for TMC: > > * arm,buffer-size: size of contiguous buffer space for TMC ETR > diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c > index 07a1367c733f..58bfd6319f65 100644 > --- a/drivers/hwtracing/coresight/coresight-cpu-debug.c > +++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c > @@ -579,6 +579,9 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id) > return -ENOMEM; > > drvdata->cpu = coresight_get_cpu(dev); > + if (drvdata->cpu < 0) > + return drvdata->cpu; > + > if (per_cpu(debug_drvdata, drvdata->cpu)) { > dev_err(dev, "CPU%d drvdata has already been initialized\n", > drvdata->cpu); > diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c > index 225c2982e4fe..e2cb6873c3f2 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x.c > @@ -816,6 +816,9 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id) > } > > drvdata->cpu = coresight_get_cpu(dev); > + if (drvdata->cpu < 0) > + return drvdata->cpu; > + > desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); > if (!desc.name) > return -ENOMEM; > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 7fe266194ab5..7bcac8896fc1 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -1101,6 +1101,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) > spin_lock_init(&drvdata->spinlock); > > drvdata->cpu = coresight_get_cpu(dev); > + if (drvdata->cpu < 0) > + return drvdata->cpu; > + > desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); > if (!desc.name) > return -ENOMEM; > diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c > index 3c5ceda8db24..4990da2c13e9 100644 > --- a/drivers/hwtracing/coresight/coresight-platform.c > +++ b/drivers/hwtracing/coresight/coresight-platform.c > @@ -159,16 +159,16 @@ static int of_coresight_get_cpu(struct device *dev) > struct device_node *dn; > > if (!dev->of_node) > - return 0; > + return -ENODEV; > + > dn = of_parse_phandle(dev->of_node, "cpu", 0); > - /* Affinity defaults to CPU0 */ > if (!dn) > - return 0; > + return -ENODEV; > + > cpu = of_cpu_node_to_id(dn); > of_node_put(dn); > > - /* Affinity to CPU0 if no cpu nodes are found */ > - return (cpu < 0) ? 0 : cpu; > + return cpu; > } Function of_coresight_get_cpu() needs to return -ENODEV rather than 0 when !CONFIG_OF > > /* > @@ -734,14 +734,14 @@ static int acpi_coresight_get_cpu(struct device *dev) > struct acpi_device *adev = ACPI_COMPANION(dev); > > if (!adev) > - return 0; > + return -ENODEV; > status = acpi_get_parent(adev->handle, &cpu_handle); > if (ACPI_FAILURE(status)) > - return 0; > + return -ENODEV; > > cpu = acpi_handle_to_logical_cpuid(cpu_handle); > if (cpu >= nr_cpu_ids) > - return 0; > + return -ENODEV; > return cpu; > } > Same as above, but for !CONFIG_ACPI Thanks, Mathieu > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >