From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Varadarajan Narayanan <varada@codeaurora.org>
Cc: agross@kernel.org, robh+dt@kernel.org, mturquette@baylibre.com,
sboyd@kernel.org, linus.walleij@linaro.org,
catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de,
nsekar@codeaurora.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, sricharan@codeaurora.org
Subject: Re: [PATCH 6/7] arm64: dts: Add ipq5018 SoC and MP03 board support
Date: Tue, 5 Jan 2021 12:55:03 -0600 [thread overview]
Message-ID: <X/S2B8HkWkFUWuUl@builder.lan> (raw)
In-Reply-To: <1601270140-4306-7-git-send-email-varada@codeaurora.org>
On Mon 28 Sep 00:15 CDT 2020, Varadarajan Narayanan wrote:
> Add initial device tree support for the Qualcomm IPQ5018 SoC and
> MP03.1-C2 board.
>
> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 ++++
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++++++++
> 4 files changed, 239 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 6031aee..694063f 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -28,6 +28,7 @@ description: |
> apq8074
> apq8084
> apq8096
> + ipq5018
> ipq6018
> ipq8074
> mdm9615
> @@ -49,6 +50,7 @@ description: |
> hk01
> idp
> liquid
> + mp03
> mtp
> qrd
> sbc
> @@ -142,6 +144,11 @@ properties:
>
> - items:
> - enum:
> + - qcom,ipq5018-mp03
> + - const: qcom,ipq5018
> +
> + - items:
> + - enum:
> - qcom,ipq8064-ap148
> - const: qcom,ipq8064
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d8f1466..3873970 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> new file mode 100644
> index 00000000..41bb3b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5018 CP01 board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5018.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
> + compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
> +
> + aliases {
> + serial0 = &blsp1_uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs-append = " swiotlb=1";
> + };
> +};
> +
> +&blsp1_uart1 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> new file mode 100644
> index 00000000..12492a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&intc>;
> +
> + clocks {
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
> + xo: xo {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x1>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
> + };
> +
> + pmuv8: pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz: tz@4ac00000 {
> + reg = <0x0 0x4ac00000 0x0 0x00400000>;
> + no-map;
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + dma-ranges;
You can't have an empty dma-ranges when the bus and the parent node has
different #address/size-cells.
See 77e9c198b155 ("arm64: dts: qcom: clear the warnings caused by empty dma-ranges")
> + compatible = "simple-bus";
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq5018-pinctrl";
> + reg = <0x01000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 80>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + serial_1_pins: serial1-pinmux {
> + pins = "gpio31", "gpio32", "gpio33", "gpio34";
> + function = "blsp1_uart1";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
> + };
> +
> + gcc: gcc@1800000 {
> + compatible = "qcom,gcc-ipq5018";
> + reg = <0x01800000 0x80000>;
> + clocks = <&xo>, <&sleep_clk>;
> + clock-names = "xo", "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + blsp1_uart1: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0x0b000000 0x1000>, /*GICD*/
> + <0x0b002000 0x1000>, /*GICC*/
> + <0x0b001000 0x1000>, /*GICH*/
> + <0x0b004000 0x1000>; /*GICV*/
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
This isn't a mmio device, so move it outside /soc
Thanks,
Bjorn
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + timer@b120000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b120000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@b120000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b121000 0x1000>,
> + <0x0b122000 0x1000>;
> + };
> +
> + frame@b123000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xb123000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b124000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b124000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b125000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b125000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b126000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b126000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b127000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b127000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b128000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b128000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +};
> --
> 2.7.4
>
next prev parent reply other threads:[~2021-01-05 18:56 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 5:15 [PATCH 0/7] Add minimal boot support for IPQ5018 Varadarajan Narayanan
2020-09-28 5:15 ` [PATCH 1/7] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs Varadarajan Narayanan
2020-10-14 2:36 ` Stephen Boyd
2020-12-26 0:51 ` Konrad Dybcio
2021-01-05 8:55 ` Varadarajan Narayanan
2020-09-28 5:15 ` [PATCH 2/7] dt-bindings: arm64: ipq5018: Add binding descriptions for clock and reset Varadarajan Narayanan
2020-09-29 19:24 ` Rob Herring
2020-09-28 5:15 ` [PATCH 4/7] dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings Varadarajan Narayanan
2020-09-28 18:10 ` Rob Herring
2020-09-29 8:15 ` Varadarajan Narayanan
2020-09-28 5:15 ` [PATCH 5/7] pinctrl: qcom: Add IPQ5018 pinctrl driver Varadarajan Narayanan
2020-09-28 18:43 ` Bjorn Andersson
2020-09-29 8:04 ` Varadarajan Narayanan
2020-09-28 5:15 ` [PATCH 6/7] arm64: dts: Add ipq5018 SoC and MP03 board support Varadarajan Narayanan
2020-10-06 18:18 ` Rob Herring
2021-01-05 18:55 ` Bjorn Andersson [this message]
2020-09-28 5:15 ` [PATCH 7/7] arm64: defconfig: Enable IPQ5018 SoC base configs Varadarajan Narayanan
[not found] ` <1601270140-4306-4-git-send-email-varada@codeaurora.org>
2020-10-14 2:28 ` [PATCH 3/7] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 Stephen Boyd
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=X/S2B8HkWkFUWuUl@builder.lan \
--to=bjorn.andersson@linaro.org \
--cc=agross@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=nsekar@codeaurora.org \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=sricharan@codeaurora.org \
--cc=varada@codeaurora.org \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).