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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id r20sm4954787otd.26.2021.03.29.20.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Mar 2021 20:22:49 -0700 (PDT) Date: Mon, 29 Mar 2021 22:22:47 -0500 From: Bjorn Andersson To: Eric Anholt Cc: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Sean Paul , Jordan Crouse , Robin Murphy , Will Deacon , Rob Herring , Joerg Roedel , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for db820c. Message-ID: References: <20210326231303.3071950-1-eric@anholt.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210326231303.3071950-1-eric@anholt.net> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote: > db820c wants to use the qcom smmu path to get HUPCF set (which keeps > the GPU from wedging and then sometimes wedging the kernel after a > page fault), but it doesn't have separate pagetables support yet in > drm/msm so we can't go all the way to the TTBR1 path. > > Signed-off-by: Eric Anholt Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > > We've been seeing a flaky test per day or so in Mesa CI where the > kernel gets wedged after an iommu fault turns into CP errors. With > this patch, the CI isn't throwing the string of CP errors on the > faults in any of the ~10 jobs I've run so far. > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > index bcda17012aee..51f22193e456 100644 > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > @@ -130,6 +130,16 @@ static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_doma > return __arm_smmu_alloc_bitmap(smmu->context_map, start, count); > } > > +static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) > +{ > + const struct device_node *np = smmu->dev->of_node; > + > + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) > + return false; > + > + return true; > +} > + > static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > struct io_pgtable_cfg *pgtbl_cfg, struct device *dev) > { > @@ -144,7 +154,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, > * be AARCH64 stage 1 but double check because the arm-smmu code assumes > * that is the case when the TTBR1 quirk is enabled > */ > - if ((smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > + if (qcom_adreno_can_do_ttbr1(smmu_domain->smmu) && > + (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) && > (smmu_domain->cfg.fmt == ARM_SMMU_CTX_FMT_AARCH64)) > pgtbl_cfg->quirks |= IO_PGTABLE_QUIRK_ARM_TTBR1; > > -- > 2.31.0 >